公开(公告)号：US20190198647A1

公开(公告)日：2019-06-27

申请号：US16287581

申请日：2019-02-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213 ,  H01L27/11531 ,  H01L29/423 ,  H01L49/02 ,  H01L27/11536

CPC classification number: H01L29/66825 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11536 ,  H01L28/00 ,  H01L29/423 ,  H01L29/42328

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US10833178B2

公开(公告)日：2020-11-10

申请号：US16576370

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L27/11521 ,  H01L27/11531 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/11536 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US10600794B2

公开(公告)日：2020-03-24

申请号：US16160812

申请日：2018-10-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Andy Liu ,  Xian Liu ,  Leo Xing ,  Melvin Diao ,  Nhan Do

IPC: H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11524 ,  H01L21/28

Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

公开(公告)号：US20200013883A1

公开(公告)日：2020-01-09

申请号：US16576389

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L21/3213 ,  H01L27/11521 ,  H01L27/11536 ,  H01L27/11531 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US10276696B2

公开(公告)日：2019-04-30

申请号：US15494499

申请日：2017-04-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/115 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/423

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US10833179B2

公开(公告)日：2020-11-10

申请号：US16576389

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L27/11521 ,  H01L27/11531 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/11536 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20200013882A1

公开(公告)日：2020-01-09

申请号：US16576348

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L21/3213 ,  H01L27/11521 ,  H01L27/11536 ,  H01L27/11531 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20190214396A1

公开(公告)日：2019-07-11

申请号：US16160812

申请日：2018-10-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Andy Liu ,  Xian Liu ,  Leo Xing ,  Melvin Diao ,  Nhan Do

IPC: H01L27/11521

Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

公开(公告)号：US11081553B2

公开(公告)日：2021-08-03

申请号：US16868143

申请日：2020-05-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo Xing ,  Chunming Wang ,  Guo Yong Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L21/00 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/788

Abstract: A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.

公开(公告)号：US20210005724A1

公开(公告)日：2021-01-07

申请号：US16796412

申请日：2020-02-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Xian Liu ,  Nhan Do ,  Leo Xing ,  Guo Yong Liu ,  Melvin Diao

IPC: H01L21/28 ,  H01L27/11521

Abstract: A method of forming a memory device that includes forming a first polysilicon layer using a first polysilicon deposition over a semiconductor substrate, forming an insulation spacer on the first polysilicon layer, and removing some of the first polysilicon layer to leave a first polysilicon block under the insulation spacer. A source region is formed in the substrate adjacent a first side surface of the first polysilicon block. A second polysilicon layer is formed using a second polysilicon deposition. The second polysilicon layer is partially removed to leave a second polysilicon block over the substrate and adjacent to a second side surface of the first polysilicon block. A third polysilicon layer is formed using a third polysilicon deposition. The third polysilicon layer is partially removed to leave a third polysilicon block over the source region. A drain region is formed in the substrate adjacent to the second polysilicon block.