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公开(公告)号：US20240088246A1
公开(公告)日：2024-03-14
申请号：US18510991
申请日：2023-11-16
发明人： Yu-Ling Hsu , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC分类号： H01L29/423 , H01L21/265 , H01L21/28 , H01L21/3213 , H01L23/522 , H01L23/528 , H01L29/40 , H01L29/66 , H01L29/788
CPC分类号： H01L29/42328 , H01L21/26513 , H01L21/32139 , H01L23/5226 , H01L23/528 , H01L29/401 , H01L29/40114 , H01L29/66825 , H01L29/7881
摘要： Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
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公开(公告)号：US11812608B2
公开(公告)日：2023-11-07
申请号：US17316278
申请日：2021-05-10
发明人： Tsun-Kai Tsao , Hung-Ling Shih , Po-Wei Liu , Shun-Shing Yang , Wen-Tuo Huang , Yong-Shiuan Tsair , ShihKuang Yang
IPC分类号： H10B41/41 , H01L21/28 , H01L29/423 , H10B41/30 , H01L21/3105
CPC分类号： H10B41/41 , H01L21/31056 , H01L29/40114 , H01L29/42328 , H10B41/30
摘要： A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.
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公开(公告)号：US20230290411A1
公开(公告)日：2023-09-14
申请号：US18321975
申请日：2023-05-23
发明人： Shih Kuang Yang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin
CPC分类号： G11C16/08 , G11C11/1657 , H10B12/053 , H10B41/30
摘要： Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
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4.发明授权公开(公告)号：US11670689B2
公开(公告)日：2023-06-06
申请号：US17471722
申请日：2021-09-10
发明人： Yu-Wen Tseng , Po-Wei Liu , Hung-Ling Shih , Tsung-Yu Yang , Tsung-Hua Yang , Yu-Chun Chang
IPC分类号： H01L29/40 , H01L29/423 , H01L29/06 , H01L29/78
CPC分类号： H01L29/401 , H01L29/0653 , H01L29/423 , H01L29/7823
摘要： A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
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公开(公告)号：US20210399103A1
公开(公告)日：2021-12-23
申请号：US17462444
申请日：2021-08-31
发明人： Yu-Ling Hsu , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC分类号： H01L29/423 , H01L23/528 , H01L23/522 , H01L29/40 , H01L21/265 , H01L29/66 , H01L29/788 , H01L21/3213 , H01L21/28
摘要： Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
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6.发明申请Methods and Apparatus for Non-Volatile Memory Cells with Increased Programming Efficiency 有权具有提高编程效率的非易失性存储器单元的方法和装置公开(公告)号：US20140151782A1
公开(公告)日：2014-06-05
申请号：US14176968
申请日：2014-02-10
发明人： Yong-Shiuan Tsair , Wen-Ting Chu , Po-Wei Liu , Wen-Tuo Huang , Yu-Hsiang Yang , Chieh-Fei Chiu , Yu-Ling Hsu
IPC分类号： H01L21/28 , H01L29/423 , H01L27/115
CPC分类号： H01L21/28273 , H01L27/11517 , H01L29/42328 , H01L29/7881
摘要： Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.
摘要翻译： 提高编程效率的非易失性存储单元的方法和装置。 公开了一种装置，其包括形成在半导体衬底上形成的浮动栅极的一部分上的控制栅极。 所述控制栅极包括邻近所述半导体衬底中的源极区域的源极侧壁间隔壁和漏极侧壁间隔物，所述浮置栅极具有邻近所述源极区域的未被所述控制栅极覆盖的上表面部分; 在源极侧壁间隔物上的多晶硅电介质和邻近源极区域的浮置栅极的上表面; 以及擦除栅极，形成在源极区域上并且覆盖多晶硅电介质并且邻近控制栅极的源极侧壁，擦除栅极覆盖邻近源极区域的浮置栅极的上表面的至少一部分。 提供了形成装置的方法。
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公开(公告)号：US12101931B2
公开(公告)日：2024-09-24
申请号：US18354881
申请日：2023-07-19
发明人： Wen-Tuo Huang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC分类号： H10B41/30 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788
CPC分类号： H10B41/30 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53271 , H01L29/401 , H01L29/40114 , H01L29/42328 , H01L29/4916 , H01L29/66825 , H01L29/788
摘要： Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
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公开(公告)号：US12068032B2
公开(公告)日：2024-08-20
申请号：US18321975
申请日：2023-05-23
发明人： Shih Kuang Yang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin
CPC分类号： G11C16/08 , G11C11/1657 , H10B12/053 , H10B41/30
摘要： Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
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公开(公告)号：US20230363155A1
公开(公告)日：2023-11-09
申请号：US18354881
申请日：2023-07-19
发明人： Wen-Tuo Huang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin , Shih Kuang Yang
IPC分类号： H10B41/30 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788
CPC分类号： H10B41/30 , H01L29/40114 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53271 , H01L29/401 , H01L29/42328 , H01L29/4916 , H01L29/66825 , H01L29/788
摘要： Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
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公开(公告)号：US11699488B2
公开(公告)日：2023-07-11
申请号：US17506904
申请日：2021-10-21
发明人： Shih Kuang Yang , Ping-Cheng Li , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang , Yu-Ling Hsu , Yong-Shiuan Tsair , Chia-Sheng Lin
CPC分类号： G11C16/08 , G11C11/1657 , H10B12/053 , H10B41/30
摘要： Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
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