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公开(公告)号：US11875249B2
公开(公告)日：2024-01-16
申请号：US17518629
申请日：2021-11-04
发明人： Siyuranga Koswatta , Yulong Li , Paul M. Solomon
摘要： Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example system includes a crosspoint array, wherein each array node represents a connection between neurons of the neural network, and wherein each node stores a weight assigned to the node. The crosspoint array includes a crosspoint device at each node. The crosspoint device includes a counter that has multiple single bit counters, and states of the counters represent the weight to be stored at the crosspoint device. Further, the crosspoint device includes a resistor device that has multiple resistive circuits, and each resistive circuit is associated with a respective counter from the counters. The resistive circuits are activated or deactivated according to a state of the associated counter, and an electrical conductance of the resistor device is adjusted based at least in part on the resistive circuits that are activated.
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公开(公告)号：US11177349B2
公开(公告)日：2021-11-16
申请号：US16747027
申请日：2020-01-20
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L29/06 , H01L29/66 , H01L29/68 , H01L29/49 , H01L29/205 , H01L29/80 , H01L27/11521 , H01L27/1159 , H01L29/51 , H01L29/78 , H01L21/28 , H01L29/165 , H01L27/108 , H01L29/788 , H01L27/24 , H01L29/423
摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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公开(公告)号：US10586849B2
公开(公告)日：2020-03-10
申请号：US16434711
申请日：2019-06-07
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L29/06 , H01L29/66 , H01L29/68 , H01L29/49 , H01L29/205 , H01L29/80 , H01L27/11521 , H01L27/1159 , H01L29/51 , H01L29/78 , H01L21/28 , H01L29/165 , H01L27/108 , H01L29/788 , H01L27/24 , H01L29/423
摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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公开(公告)号：US12015056B2
公开(公告)日：2024-06-18
申请号：US18306359
申请日：2023-04-25
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L21/28 , H01L29/06 , H01L29/165 , H01L29/205 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/68 , H01L29/78 , H01L29/788 , H01L29/80 , H10B12/00 , H10B41/30 , H10B51/30 , H10B63/00
CPC分类号： H01L29/1045 , H01L29/0646 , H01L29/1054 , H01L29/165 , H01L29/205 , H01L29/40111 , H01L29/40114 , H01L29/42324 , H01L29/4983 , H01L29/516 , H01L29/66431 , H01L29/66659 , H01L29/66977 , H01L29/685 , H01L29/785 , H01L29/7881 , H01L29/802 , H10B12/30 , H10B41/30 , H10B51/30 , H10B63/00 , H01L29/66825 , H01L29/6684 , H01L29/78391 , H01L29/788
摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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公开(公告)号：US20230268396A1
公开(公告)日：2023-08-24
申请号：US18306359
申请日：2023-04-25
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L29/06 , H01L29/66 , H01L29/68 , H01L29/49 , H01L29/205 , H01L29/80 , H01L29/51 , H01L29/78 , H01L21/28 , H01L29/165 , H01L29/788 , H01L29/423 , H10B12/00 , H10B41/30 , H10B51/30 , H10B63/00
CPC分类号： H01L29/1045 , H01L29/0646 , H01L29/66977 , H01L29/685 , H01L29/4983 , H01L29/205 , H01L29/1054 , H01L29/66431 , H01L29/66659 , H01L29/802 , H01L29/516 , H01L29/785 , H01L29/40111 , H01L29/165 , H01L29/40114 , H01L29/7881 , H01L29/42324 , H10B12/30 , H10B41/30 , H10B51/30 , H10B63/00 , H01L29/6684 , H01L29/78391 , H01L29/66825 , H01L29/788
摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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公开(公告)号：US11855149B2
公开(公告)日：2023-12-26
申请号：US17474260
申请日：2021-09-14
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L29/06 , H01L29/66 , H01L29/68 , H01L29/49 , H01L29/205 , H01L29/80 , H01L29/51 , H01L29/78 , H01L21/28 , H01L29/165 , H01L29/788 , H01L29/423 , H10B12/00 , H10B41/30 , H10B51/30 , H10B63/00
CPC分类号： H01L29/1045 , H01L29/0646 , H01L29/1054 , H01L29/165 , H01L29/205 , H01L29/40111 , H01L29/40114 , H01L29/42324 , H01L29/4983 , H01L29/516 , H01L29/66431 , H01L29/66659 , H01L29/66977 , H01L29/685 , H01L29/785 , H01L29/7881 , H01L29/802 , H10B12/30 , H10B41/30 , H10B51/30 , H10B63/00 , H01L29/6684 , H01L29/66825 , H01L29/788 , H01L29/78391
摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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公开(公告)号：US11222259B2
公开(公告)日：2022-01-11
申请号：US15840322
申请日：2017-12-13
发明人： Siyuranga Koswatta , Yulong Li , Paul M. Solomon
摘要： Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example method includes setting a state of each single bit counter from a set of single bit counters in the crosspoint device, the states of the single bit counters representing the weight to be stored at the crosspoint device. The method further includes adjusting electrical conductance of a resistor device of the crosspoint device. The resistor device includes a set of resistive circuits, each resistive circuit associated with a respective single bit counter from the set of single bit counters, the electrical conductance adjusted by activating or deactivating each resistive circuit according to a state of the associated single bit counter.
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公开(公告)号：US20210408240A1
公开(公告)日：2021-12-30
申请号：US17474260
申请日：2021-09-14
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L29/06 , H01L29/66 , H01L29/68 , H01L29/49 , H01L29/205 , H01L29/80 , H01L27/11521 , H01L27/1159 , H01L29/51 , H01L29/78 , H01L21/28 , H01L29/165 , H01L27/108 , H01L29/788 , H01L27/24 , H01L29/423
摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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公开(公告)号：US20220058474A1
公开(公告)日：2022-02-24
申请号：US17518629
申请日：2021-11-04
发明人： Siyuranga Koswatta , Yulong Li , Paul M. Solomon
摘要： Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example system includes a crosspoint array, wherein each array node represents a connection between neurons of the neural network, and wherein each node stores a weight assigned to the node. The crosspoint array includes a crosspoint device at each node. The crosspoint device includes a counter that has multiple single bit counters, and states of the counters represent the weight to be stored at the crosspoint device. Further, the crosspoint device includes a resistor device that has multiple resistive circuits, and each resistive circuit is associated with a respective counter from the counters. The resistive circuits are activated or deactivated according to a state of the associated counter, and an electrical conductance of the resistor device is adjusted based at least in part on the resistive circuits that are activated.
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公开(公告)号：US20200152741A1
公开(公告)日：2020-05-14
申请号：US16747027
申请日：2020-01-20
发明人： Yulong Li , Paul M. Solomon , Siyuranga Koswatta
IPC分类号： H01L29/10 , H01L29/80 , H01L29/66 , H01L29/205 , H01L29/49 , H01L29/68 , H01L29/06 , H01L29/423 , H01L27/24 , H01L29/788 , H01L27/108 , H01L21/28 , H01L29/165 , H01L29/78 , H01L29/51 , H01L27/1159 , H01L27/11521
摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
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