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    Integrated circuit devices and methods of manufacturing the same
    1.
    发明授权
    Integrated circuit devices and methods of manufacturing the same 有权

    公开(公告)号：US11189632B2

    公开(公告)日：2021-11-30

    申请号：US16675273

    申请日：2019-11-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jang-Gn Yun ,  Jae-Duk Lee ,  Jai-Hyuk Song

    IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11568

    Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.

    Semiconductor device including dummy patterns and peripheral interconnection patterns at the same level
    2.
    发明授权
    Semiconductor device including dummy patterns and peripheral interconnection patterns at the same level 有权

    公开(公告)号：US11127679B2

    公开(公告)日：2021-09-21

    申请号：US17060142

    申请日：2020-10-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jang-Gn Yun ,  Jaesun Yun ,  Joon-Sung Lim

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L27/06 ,  H01L27/11573 ,  H01L27/11582

    Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.

    Vertical memory devices
    4.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US10332900B2

    公开(公告)日：2019-06-25

    申请号：US15801551

    申请日：2017-11-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Su-Ok Yun ,  Jang-Gn Yun ,  Joon-Sung Lim ,  Sung-Min Hwang

    IPC: H01L21/28 ,  H01L27/115 ,  H01L23/522 ,  H01L23/535 ,  H01L29/423 ,  H01L29/49 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575

    Abstract: A vertical memory device includes a gate structure on a peripheral circuit region of a substrate, the substrate including a cell region and the peripheral circuit region, and the gate structure including a first gate electrode, second, third, and fourth gate electrodes sequentially disposed at a plurality of levels, respectively, on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a first epitaxial layer extending through the second gate electrode on the cell region of the substrate, a channel extending through the third and fourth gate electrodes in the vertical direction on the first epitaxial layer, and a second epitaxial layer on a portion of the peripheral circuit region of the substrate adjacent the gate structure.

    Semiconductor devices and methods for forming the same
    7.
    发明授权
    Semiconductor devices and methods for forming the same 有权

    公开(公告)号：US10910398B2

    公开(公告)日：2021-02-02

    申请号：US16165426

    申请日：2018-10-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

    Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

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