公开(公告)号：US11889700B2

公开(公告)日：2024-01-30

申请号：US17220340

申请日：2021-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong Lee ,  Seorim Moon ,  Bongsoo Kang ,  Kyungjae Park ,  Cheol Ryou

IPC: H10B43/50 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

公开(公告)号：US20210399005A1

公开(公告)日：2021-12-23

申请号：US17220340

申请日：2021-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong Lee ,  Seorim Moon ,  Bongsoo Kang ,  Kyungjae Park ,  Cheol Ryou

IPC: H01L27/11575 ,  H01L23/535 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

公开(公告)号：US10431593B2

公开(公告)日：2019-10-01

申请号：US15860082

申请日：2018-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Kyoil Koo ,  Hoosung Cho ,  Sunyoung Kim ,  Cheol Ryou ,  Jaesun Yun

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/1157

Abstract: Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.