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    METHODS AND DEVICES OF CORRECTING LAYOUT FOR SEMICONDUCTOR PROCESSES USING MACHINE LEARNING
    2.
    发明申请
    METHODS AND DEVICES OF CORRECTING LAYOUT FOR SEMICONDUCTOR PROCESSES USING MACHINE LEARNING 有权

    公开(公告)号：US20220171913A1

    公开(公告)日：2022-06-02

    申请号：US17380200

    申请日：2021-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sooyong Lee ,  Jeeyong Lee ,  Seunghune Yang ,  Hyeyoung Ji

    IPC: G06F30/398 ,  G06N20/00

    Abstract: With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210399005A1

    公开(公告)日：2021-12-23

    申请号：US17220340

    申请日：2021-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sooyong Lee ,  Seorim Moon ,  Bongsoo Kang ,  Kyungjae Park ,  Cheol Ryou

    IPC: H01L27/11575 ,  H01L23/535 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

    Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

    RESIST PATTERN PREDICTION DEVICE AND RESIST PATTERN PREDICTION DEVICE CONSTRUCTION SYSTEM
    6.
    发明申请
    RESIST PATTERN PREDICTION DEVICE AND RESIST PATTERN PREDICTION DEVICE CONSTRUCTION SYSTEM 有权

    公开(公告)号：US20250076772A1

    公开(公告)日：2025-03-06

    申请号：US18665030

    申请日：2024-05-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanveen Koh ,  Kyoungyoon Park ,  Taehyung Yoo ,  Sooyong Lee

    IPC: G03F7/00

    Abstract: Disclosed is a resist pattern prediction device, which includes an optical proximity correction module for generating both an optical proximity correction and a non-optical proximity correction. The optical proximity correction module generates an aerial image by performing an optical proximity correction based on a mask image. The module also generates a resist image by performing a non-optical proximity correction on the mask image and the aerial image. The resist pattern prediction device also includes a pattern prediction module that predicts information with respect to a resist pattern based on the resist image. The non-optical proximity correction includes performing a convolution operation on the aerial image using a Volterra kernel based on a coefficient of a quadratic term of a Volterra series.

    Methods and devices of correcting layout for semiconductor processes using machine learning
    7.
    发明授权
    Methods and devices of correcting layout for semiconductor processes using machine learning 有权

    公开(公告)号：US12086526B2

    公开(公告)日：2024-09-10

    申请号：US17380200

    申请日：2021-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sooyong Lee ,  Jeeyong Lee ,  Seunghune Yang ,  Hyeyoung Ji

    IPC: G06F30/398 ,  G06N20/00

    CPC classification number: G06F30/398 ,  G06N20/00

    Abstract: With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.

    PROCESS PROXIMITY CORRECTION METHOD BASED ON MACHINE LEARNING, OPTICAL PROXIMITY CORRECTION METHOD INCLUDING THE SAME, AND METHOD OF MANUFACTURING MASK BY USING THE PROCESS PROXIMITY CORRECTION METHOD
    10.
    发明公开
    PROCESS PROXIMITY CORRECTION METHOD BASED ON MACHINE LEARNING, OPTICAL PROXIMITY CORRECTION METHOD INCLUDING THE SAME, AND METHOD OF MANUFACTURING MASK BY USING THE PROCESS PROXIMITY CORRECTION METHOD 审中-公开

    公开(公告)号：US20240319580A1

    公开(公告)日：2024-09-26

    申请号：US18529781

    申请日：2023-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeyong Jeong ,  Bonhyun Gu ,  Sooyong Lee

    IPC: G03F1/36 ,  G03F1/84

    CPC classification number: G03F1/36 ,  G03F1/84

    Abstract: The present disclosure relates to process proximity correction (PPC) methods based on machine learning (ML), optical proximity correction (OPC) methods, and mask manufacturing methods including the PPC methods. One example PPC method based on ML includes obtaining a pattern gauge-based bottom critical dimension (CD) and obtaining pattern gauge-based features from a first layout, performing a gauge clustering operation of grouping and classifying pattern gauges including similar features, calculating distribution parameters in a skew-normal distribution of the pattern gauge-based bottom CD in each cluster, performing ML between the distribution parameters and a feature in each cluster to generate a prediction ML model, predicting a distribution, a maximum limit, and a minimum limit of the pattern gauge-based bottom CD by using the prediction ML model, generating an after cleaning inspection (ACI) target including a maximum process window, and generating a second layout by performing an development inspection (ADI) retarget operation.

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