公开(公告)号：US12237265B2

公开(公告)日：2025-02-25

申请号：US18321917

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L29/786 ,  H10B12/00

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US20220262731A1

公开(公告)日：2022-08-18

申请号：US17487460

申请日：2021-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Hyunseo Shin ,  Seokhan Park ,  Seunghune Yang

IPC: H01L23/528 ,  H01L27/108

Abstract: A semiconductor device may include a gate structure, first and second source/drain layers, first and second contact plugs, first and second conductive structures, and a third contact plug. The gate structure may be on a substrate. The first and second source/drain layers may be at upper portions, respectively, of the substrate on opposite sidewalls of the gate structure and adjacent thereto. The first and second contact plugs may be on the first and second source/drain layers, respectively, and each contact plugs may extend in a vertical direction. The first and second conductive structures may contact upper surfaces of the first and second contact plugs, respectively. The third contact plug may contact an upper surface of the second conductive structure. A height and a width of the second conductive structure may be greater than a height and a width of the first conductive structure.

公开(公告)号：US09476840B2

公开(公告)日：2016-10-25

申请号：US14340910

申请日：2014-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiho Yang ,  Seunghune Yang ,  Sibo Cai

IPC: G01N21/956 ,  G06K9/46 ,  G06T11/60 ,  G01N21/88 ,  G03F7/20 ,  G06T7/00

CPC classification number: G01N21/956 ,  G01N21/88 ,  G01N21/8851 ,  G03F7/70616 ,  G06K9/4604 ,  G06T7/0006 ,  G06T7/001 ,  G06T11/60 ,  G06T2207/20221 ,  G06T2207/30148

Abstract: Inventive concepts provide a method of inspecting a semiconductor device including obtaining inspection image data of an inspection pattern of an inspection layer on a substrate. The method may include extracting inspection contour data including an inspection pattern contour from the inspection image data, and merging the inspection contour data with comparison contour data of a comparison layer to obtain merged data. The comparison layer may overlap the inspection layer. The method may also include determining a horizontal distance between the inspection pattern contour and a comparison pattern contour of the comparison contour data based on the merged data.

Abstract translation: 本发明的概念提供了一种检查半导体器件的方法，包括获得在衬底上检查层的检查图案的检查图像数据。 该方法可以包括从检查图像数据提取包括检查图案轮廓的检查轮廓数据，并且将检查轮廓数据与比较层的比较轮廓数据合并以获得合并的数据。 比较层可以与检查层重叠。 该方法还可以包括基于合并的数据确定检查图案轮廓和比较轮廓数据的比较花样轮廓之间的水平距离。

公开(公告)号：US12044961B2

公开(公告)日：2024-07-23

申请号：US17188140

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pilsoo Kang ,  Wonchan Lee ,  Sangwook Kim ,  Sungyong Moon ,  Seunghune Yang ,  Jeeeun Jung

IPC: G03F1/70 ,  G03F1/24 ,  G03F1/36 ,  H01L21/033

CPC classification number: G03F1/70 ,  G03F1/24 ,  H01L21/0334 ,  G03F1/36

Abstract: A mask forming method includes providing preliminary mask data including a Manhattan path such as a quadrangle, a bar, a polygon or a combination thereof based on a layout. Mask data including a curvilinear shape is prepared by correcting the preliminary mask data through application of an elliptical function, a B-spline curve, or a combination thereof. A mask pattern is formed on a mask substrate based on the mask data.

公开(公告)号：US11688687B2

公开(公告)日：2023-06-27

申请号：US17198591

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H10B12/03 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34 ,  H10B12/48 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50 ,  H01L21/76807 ,  H10B12/053

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US11506983B2

公开(公告)日：2022-11-22

申请号：US17185140

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hungbae Ahn ,  Sangoh Park ,  Seunghune Yang

IPC: G03F7/20 ,  H01L27/02

Abstract: A method of manufacturing a mask may include identifying an error pattern of final patterns formed on a substrate, correcting a first target pattern on the basis of the error pattern, fracturing a first mask layout into a plurality of first segments on the basis of the corrected first target pattern, and correcting the first mask layout by biasing a plurality of first target segments corresponding to a first final target among the plurality of segments. The first mask layout may include a first extension pattern, final targets disposed in zigzags, and the first final target corresponding to the error pattern, and each of the plurality of first segments may corresponds to one of the final targets.

公开(公告)号：US20220037251A1

公开(公告)日：2022-02-03

申请号：US17198591

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US20250138431A1

公开(公告)日：2025-05-01

申请号：US18677041

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Nam ,  Seongjeon Choi ,  Seunghune Yang

IPC: G03F7/00

Abstract: A method of configuring an extreme ultraviolet (EUV) light source includes obtaining first information about a mask pattern, generating a top-hat illumination system for the mask pattern based on a Fourier approximation, storing second information about aerial images of EUV point light sources that correspond to pupil mirrors, selecting a combination of the EUV point light sources according to established rules, and performing a simulation on an entire EUV illumination system, based on the selected combination of the EUV point light sources.

公开(公告)号：US20230290727A1

公开(公告)日：2023-09-14

申请号：US18321917

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H10B12/03 ,  H10B12/34 ,  H10B12/48 ,  H10B12/50 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/485 ,  H01L21/76807 ,  H10B12/053

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US20230161937A1

公开(公告)日：2023-05-25

申请号：US17951580

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Somin Cheon ,  Joonsung Kim ,  Jaewan Song ,  Seunghune Yang ,  Sooyong Lee

IPC: G06F30/3323 ,  G03F7/20

CPC classification number: G06F30/3323 ,  G03F7/70433 ,  G03F7/705 ,  G06F2119/18

Abstract: A mask layout design method capable of quickly and effectively designing a crack-resistant mask layout in a full-chip scale, a mask manufacturing method including the mask layout design method, and a mask layout are provided. The mask layout design method includes designing a full-chip layout with respect to a mask; extracting a representative pattern from the full-chip layout; detecting a stress weak point in the representative pattern; verifying the stress weak point by forming a pattern on a wafer; and changing a design rule with respect to the full-chip layout.