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    PROCESS PROXIMITY CORRECTION METHOD BASED ON MACHINE LEARNING, OPTICAL PROXIMITY CORRECTION METHOD INCLUDING THE SAME, AND METHOD OF MANUFACTURING MASK BY USING THE PROCESS PROXIMITY CORRECTION METHOD
    1.
    发明公开
    PROCESS PROXIMITY CORRECTION METHOD BASED ON MACHINE LEARNING, OPTICAL PROXIMITY CORRECTION METHOD INCLUDING THE SAME, AND METHOD OF MANUFACTURING MASK BY USING THE PROCESS PROXIMITY CORRECTION METHOD 审中-公开

    公开(公告)号：US20240319580A1

    公开(公告)日：2024-09-26

    申请号：US18529781

    申请日：2023-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeyong Jeong ,  Bonhyun Gu ,  Sooyong Lee

    IPC: G03F1/36 ,  G03F1/84

    CPC classification number: G03F1/36 ,  G03F1/84

    Abstract: The present disclosure relates to process proximity correction (PPC) methods based on machine learning (ML), optical proximity correction (OPC) methods, and mask manufacturing methods including the PPC methods. One example PPC method based on ML includes obtaining a pattern gauge-based bottom critical dimension (CD) and obtaining pattern gauge-based features from a first layout, performing a gauge clustering operation of grouping and classifying pattern gauges including similar features, calculating distribution parameters in a skew-normal distribution of the pattern gauge-based bottom CD in each cluster, performing ML between the distribution parameters and a feature in each cluster to generate a prediction ML model, predicting a distribution, a maximum limit, and a minimum limit of the pattern gauge-based bottom CD by using the prediction ML model, generating an after cleaning inspection (ACI) target including a maximum process window, and generating a second layout by performing an development inspection (ADI) retarget operation.

    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY SYSTEM
    3.
    发明公开
    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240264934A1

    公开(公告)日：2024-08-08

    申请号：US18426975

    申请日：2024-01-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungho PARK ,  Insu kim ,  Beomkyu Shin ,  Jaeyong Jeong

    IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16

    CPC classification number: G06F12/0246 ,  G06F12/0882 ,  G06F13/1668 ,  G06F2212/7201

    Abstract: In some embodiments, the memory system for communicating with a host includes a non-volatile memory device storing first mapping information, a volatile memory device storing second mapping information, and a memory controller. The first mapping information indicates a relationship between a logical address and a portion of a first physical address. The first physical address indicates a location where user data is stored. The second mapping information indicates a second relationship between the logical address and a second physical address that corresponds to a remaining portion of the first physical address. The memory controller is configured to obtain a target logical address that has been received from the host, and determine, based on the second mapping information, a target second physical address mapped to the target logical address. The non-volatile memory device is configured to obtain a target first physical address by using the first mapping information.

    Non-volatile memory device and programming method thereof
    4.
    发明授权
    Non-volatile memory device and programming method thereof 有权

    公开(公告)号：US11164643B2

    公开(公告)日：2021-11-02

    申请号：US16686567

    申请日：2019-11-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byungsoo Kim ,  Wandong Kim ,  Jaeyong Jeong

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C11/56 ,  G11C16/26

    Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

    Nonvolatile memory system that erases memory cells when changing their mode of operation
    5.
    发明授权
    Nonvolatile memory system that erases memory cells when changing their mode of operation 有权

    公开(公告)号：US10115466B2

    公开(公告)日：2018-10-30

    申请号：US15687564

    申请日：2017-08-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Wook Park ,  Kitae Park ,  Jaeyong Jeong

    IPC: G11C11/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26

    Abstract: An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.

    Non-volatile memory device and related method of operation
    6.
    发明授权
    Non-volatile memory device and related method of operation 有权
    非易失性存储器件及相关操作方法

    公开(公告)号：US09576672B2

    公开(公告)日：2017-02-21

    申请号：US14617976

    申请日：2015-02-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeyong Jeong ,  Ju Seok Lee

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/34 ,  G11C16/24

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/3454

    Abstract: A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.

    Abstract translation: 非易失性存储器件包括连接到全位线结构中的多个位线的单元阵列，连接到多个位线的寻址缓冲器电路以及被配置为控制页缓冲器电路的控制逻辑。 控制逻辑控制页面缓冲电路以在第一读取模式中感测与选定页面的偶数和偶数列对应的存储器单元，并且读取对应于偶数和奇数列之一的存储器单元 的第二读取模式。 在第一读取模式下执行感测操作至少两次，并且在第二读取模式中执行一次感测操作。

    Method for operating non-volatile memory device and memory controller
    9.
    发明授权
    Method for operating non-volatile memory device and memory controller 有权
    操作非易失性存储器件和存储器控制器的方法

    公开(公告)号：US09117536B2

    公开(公告)日：2015-08-25

    申请号：US14088511

    申请日：2013-11-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Jun Yoon ,  Jaeyong Jeong ,  Myung-Hoon Choi ,  Kitae Park

    IPC: G11C11/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3422

    Abstract: An operating method for a non-volatile memory device includes applying first and second read voltages to a first word line to perform a read operation; counting first memory cells each having a threshold voltage belonging to a first voltage range between the first read voltage and the second read voltage; applying a third read voltage to the first word line sequentially after applying the second read voltage to count second memory cells each having a second threshold voltage belonging to a voltage range between the second read voltage and the third read voltage; comparing the number of first memory cells counted and the number of second memory cells counted; determining a fourth read voltage based on a result of the comparing; and applying the fourth read voltage to the first word line sequentially after applying the third read voltage.

    Abstract translation: 一种用于非易失性存储器件的操作方法包括：将第一和第二读取电压施加到第一字线以执行读取操作; 计数每个具有属于第一读取电压和第二读取电压之间的第一电压范围的阈值电压的第一存储器单元; 在施加第二读取电压以对具有属于第二读取电压和第三读取电压之间的电压范围的第二阈值电压的第二存储器单元计数时，顺序地向第一字线施加第三读取电压; 比较计数的第一存储器单元的数量和计数的第二存储单元的数量; 基于所述比较的结果确定第四读取电压; 以及在施加第三读取电压之后，将第四读取电压顺序地施加到第一字线。

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