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    METHODS AND DEVICES OF CORRECTING LAYOUT FOR SEMICONDUCTOR PROCESSES USING MACHINE LEARNING
    1.
    发明申请
    METHODS AND DEVICES OF CORRECTING LAYOUT FOR SEMICONDUCTOR PROCESSES USING MACHINE LEARNING 有权

    公开(公告)号：US20220171913A1

    公开(公告)日：2022-06-02

    申请号：US17380200

    申请日：2021-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sooyong Lee ,  Jeeyong Lee ,  Seunghune Yang ,  Hyeyoung Ji

    IPC: G06F30/398 ,  G06N20/00

    Abstract: With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.

    Manufacturing method of semiconductor device
    2.
    发明授权
    Manufacturing method of semiconductor device 有权

    公开(公告)号：US11562934B2

    公开(公告)日：2023-01-24

    申请号：US16992271

    申请日：2020-08-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sooyong Lee ,  Mincheol Kang ,  Bongsoo Kang ,  Jeeyong Lee

    IPC: H01L21/66 ,  H01L27/11556 ,  G06N3/08 ,  G06N3/04 ,  H01L27/11582

    Abstract: A method of manufacturing a semiconductor device includes forming a lower mold having lower layers stacked on a substrate and lower channel structures passing therethrough; forming an upper mold including upper layers stacked on the lower mold and upper channel structures passing therethrough; removing the upper mold to expose an upper surface of the lower mold; separating an upper original image in which traces of the upper channel structures are displayed, and a lower original image in which the lower channel structures are displayed, from an original image capturing the upper surface of the lower mold; inputting the upper original image into a learned neural network to acquire an upper restored image in which cross sections of the upper channel structures are displayed; and comparing the upper restored image with the lower original image to verify an alignment state of the upper and lower molds.

    Methods and devices of correcting layout for semiconductor processes using machine learning
    5.
    发明授权
    Methods and devices of correcting layout for semiconductor processes using machine learning 有权

    公开(公告)号：US12086526B2

    公开(公告)日：2024-09-10

    申请号：US17380200

    申请日：2021-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sooyong Lee ,  Jeeyong Lee ,  Seunghune Yang ,  Hyeyoung Ji

    IPC: G06F30/398 ,  G06N20/00

    CPC classification number: G06F30/398 ,  G06N20/00

    Abstract: With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.

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