公开(公告)号：US09899408B2

公开(公告)日：2018-02-20

申请号：US15189205

申请日：2016-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwan Son ,  Young-Woo Park ,  Jae-Duk Lee

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.

公开(公告)号：US11411024B2

公开(公告)日：2022-08-09

申请号：US16995084

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun Lee ,  Jae-Hoon Jang ,  Jae-Duk Lee ,  Joon-Hee Lee ,  Young-Jin Jung

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/308 ,  H01L21/28 ,  H01L27/11565

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

公开(公告)号：US11189632B2

公开(公告)日：2021-11-30

申请号：US16675273

申请日：2019-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Jae-Duk Lee ,  Jai-Hyuk Song

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11568

Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.

公开(公告)号：US09659959B2

公开(公告)日：2017-05-23

申请号：US15334968

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Duk Lee ,  Young-Woo Park

IPC: H01L21/336 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L23/528

CPC classification number: H01L21/02636 ,  H01L21/28282 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

公开(公告)号：US10199389B2

公开(公告)日：2019-02-05

申请号：US15485334

申请日：2017-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/528

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

公开(公告)号：US09646984B2

公开(公告)日：2017-05-09

申请号：US15264902

申请日：2016-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee

IPC: H01L27/115 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11582

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

公开(公告)号：US20240268110A1

公开(公告)日：2024-08-08

申请号：US18640528

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-Cheol Shin ,  Young-Woo Park ,  Jae-Duk Lee

IPC: H10B43/20 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/20 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/20 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US11074981B2

公开(公告)日：2021-07-27

申请号：US17092896

申请日：2020-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Gn Yun ,  Jae-Duk Lee

IPC: G11C16/14 ,  G11C16/04

Abstract: An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.

公开(公告)号：US10832781B2

公开(公告)日：2020-11-10

申请号：US16550591

申请日：2019-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Gn Yun ,  Jae-Duk Lee

IPC: G11C16/14 ,  G11C16/04

Abstract: An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.

公开(公告)号：US10770473B2

公开(公告)日：2020-09-08

申请号：US16122037

申请日：2018-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun Lee ,  Jae-Hoon Jang ,  Jae-Duk Lee ,  Joon-Hee Lee ,  Young-Jin Jung

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/308 ,  H01L21/28 ,  H01L27/11565

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.