公开(公告)号：US09202571B2

公开(公告)日：2015-12-01

申请号：US14272765

申请日：2014-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

IPC: G11C11/34 ,  G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157

Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Abstract translation: 非易失性存储器件利用垂直堆叠的非易失性存储器单元串（例如，NAND型串），其可选择性地耦合到衬底内的公共源极线。 该选择耦合可以由具有不同阈值电压的横向接地选择晶体管提供，这些阈值电压考虑了非垂直堆叠的非易失性存储单元串与公共源极线之间的不同横向间隔。

公开(公告)号：US09000508B2

公开(公告)日：2015-04-07

申请号：US14024844

申请日：2013-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun Lee ,  Sunhil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  G11C16/28 ,  H01L27/115 ,  H01L29/788

CPC classification number: G11C16/28 ,  G11C16/14 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

Abstract: Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

Abstract translation: 根据本发明的实施例的非易失性存储器件包括高度集成的非易失性存储器单元的垂直堆叠。 这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串 系列。

公开(公告)号：US08901745B2

公开(公告)日：2014-12-02

申请号：US13771526

申请日：2013-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L27/115

CPC classification number: H01L21/768 ,  H01L23/5226 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

Abstract translation: 三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。 薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面 离衬底更远。 多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。 还讨论了相关方法。

公开(公告)号：US20130201758A1

公开(公告)日：2013-08-08

申请号：US13836212

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doogon Kim ,  Sunil Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jaehun Jeong

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

Abstract: Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.

Abstract translation: 提供了一种操作非易失性存储器件的方法。 该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到 与第一和第二NAND串的存储单元相连的字线。

公开(公告)号：US12088751B2

公开(公告)日：2024-09-10

申请号：US17897329

申请日：2022-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongkeun Kim ,  Yonghwa Han ,  Myungchul Ryu ,  Sukjin Yun ,  Jaehoon Jang

IPC: G06F1/16 ,  F16C11/04 ,  H04M1/02 ,  E05D3/18

CPC classification number: H04M1/0268 ,  F16C11/04 ,  G06F1/1641 ,  H04M1/0214 ,  E05D3/18 ,  E05Y2999/00

Abstract: An electronic device includes a display, and a hinge assembly foldable together with the display and corresponding to a folding area of the display. The hinge assembly includes a hinge bracket defining first and second hinge axes, first and second rotators connected to the hinge bracket and respectively rotatable about the first and second hinge axes, first and second sliders connected to the hinge bracket, respectively slidable relative to the hinge bracket in a direction parallel with the hinge axes, and spaced apart from each other in the direction, and an elastic member between the first and second sliders and providing an elastic force in the direction. The first and second rotators respectively include first and second helical structures having a helical shape with the first and second hinge axes as a center, and are each connected to the first and second sliders through the first and second helical structures.

公开(公告)号：US20180240808A1

公开(公告)日：2018-08-23

申请号：US15714254

申请日：2017-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyeong SONG ,  Chadong Yeo ,  Jaeduk Lee ,  Jaehoon Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/12

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.

公开(公告)号：US09331095B2

公开(公告)日：2016-05-03

申请号：US14921845

申请日：2015-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

IPC: G11C11/34 ,  H01L27/115 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157

Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

公开(公告)号：US20160056172A1

公开(公告)日：2016-02-25

申请号：US14921845

申请日：2015-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157

Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Abstract translation: 非易失性存储器件利用垂直堆叠的非易失性存储器单元串（例如，NAND型串），其可选择性地耦合到衬底内的公共源极线。 该选择耦合可以由具有不同阈值电压的横向接地选择晶体管提供，这些阈值电压考虑了非垂直堆叠的非易失性存储单元串与公共源极线之间的不同横向间隔。

公开(公告)号：US08743614B2

公开(公告)日：2014-06-03

申请号：US14095597

申请日：2013-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

IPC: G11C11/34

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157

Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Abstract translation: 非易失性存储器件利用垂直堆叠的非易失性存储器单元串（例如，NAND型串），其可选择性地耦合到衬底内的公共源极线。 该选择耦合可以由具有不同阈值电压的横向接地选择晶体管提供，这些阈值电压考虑了非垂直堆叠的非易失性存储单元串与公共源极线之间的不同横向间隔。

公开(公告)号：US11495615B2

公开(公告)日：2022-11-08

申请号：US17009075

申请日：2020-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungeun Park ,  Jae-Joo Shim ,  Dongsung Woo ,  Jongkwang Lim ,  Jaehoon Jang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11539 ,  H01L27/11565

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.