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    Three-dimensional semiconductor memory device
    1.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11495615B2

    公开(公告)日：2022-11-08

    申请号：US17009075

    申请日：2020-09-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungeun Park ,  Jae-Joo Shim ,  Dongsung Woo ,  Jongkwang Lim ,  Jaehoon Jang

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11539 ,  H01L27/11565

    Abstract: Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.

    Methods of manufacturing vertical memory devices at an edge region
    2.
    发明授权
    Methods of manufacturing vertical memory devices at an edge region 有权

    公开(公告)号：US10008389B2

    公开(公告)日：2018-06-26

    申请号：US15408926

    申请日：2017-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joo-Heon Kang ,  Jae-Joo Shim

    IPC: H01L21/311 ,  H01L27/11582

    CPC classification number: H01L21/31144 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    Abstract: A method of manufacturing a vertical memory device includes forming a preliminary first mold structure on a substrate, which includes main and edge regions, and the first preliminary mold structure including alternating insulation and sacrificial layers, forming a first mask on the preliminary first mold structure to expose the preliminary first mold structure between a boundary of the substrate and a first target position, partially etching the insulation and sacrificial layers using the first mask to form a preliminary second mold structure, forming a second mask on the preliminary second mold structure to expose the preliminary second mold structure between the boundary of the substrate and a second target position different from the first target position, and partially etching the insulation layers and the sacrificial layers using the second mask.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    3.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240098990A1

    公开(公告)日：2024-03-21

    申请号：US18127404

    申请日：2023-03-28

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Sung-Min Hwang ,  Jaehoon Lee ,  Seunghyun Cho ,  Jae-Joo Shim ,  Dong-Sik Lee

    IPC: H01L29/76 ,  H01L23/528

    CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35

    Abstract: A semiconductor device includes a gate stack structure including insulating patterns and conductive patterns which are alternately stacked, a first separation structure penetrating the gate stack structure, a second separation structure penetrating the gate stack structure and being adjacent to the first separation structure, first and second memory channel structures penetrating the gate stack structure and disposed between the first separation structure and the second separation structure, a first bit line overlapping with the first and second memory channel structures and electrically connected to the first memory channel structure, and a second bit line overlapping with the first and second memory channel structures and the first bit line and electrically connected to the second memory channel structure.

    Vertical semiconductor devices
    4.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US10825830B2

    公开(公告)日：2020-11-03

    申请号：US16392958

    申请日：2019-04-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tae-Chul Jung ,  Bong-Tae Park ,  Jae-Joo Shim

    IPC: H01L23/528 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768

    Abstract: A vertical semiconductor device includes a substrate with a first and second region. A conductive pattern on the first region extends in a first direction. The first region includes a cell region, a first dummy region and a second dummy region. The conductive pattern extends in a first direction. A pad is disposed on the second region, the pad contacts a side of the conductive pattern. A plurality of first dummy structures extends through the conductive pattern on the first dummy region. A plurality of second dummy structures extend through the conductive pattern on the second dummy region, the second dummy structures disposed in a plurality of columns that extend in a second direction perpendicular to the first direction. Widths of upper surfaces of the second dummy structures are different in each column, and the widths of upper surfaces of the second dummy structures increase toward the second region.

    Three-dimensional semiconductor memory devices
    7.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10784281B2

    公开(公告)日：2020-09-22

    申请号：US16425349

    申请日：2019-05-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joo-Heon Kang ,  Bongtae Park ,  Jae-Joo Shim

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/311 ,  H01L27/1157

    Abstract: A 3D semiconductor memory device includes an electrode structure on a substrate, the electrode structure including gate electrodes stacked in a first direction perpendicular to a top surface of the substrate, a vertical semiconductor pattern penetrating the electrode structure and connected to the substrate, and a data storage pattern between the electrode structure and the vertical semiconductor pattern. The data storage pattern includes first, second and third insulating patterns sequentially stacked. Each of the first to third insulating patterns includes a horizontal portion extending in a second direction parallel to the top surface of the substrate. The horizontal portions of the first, second and third insulating patterns are sequentially stacked in the first direction. At least one of the horizontal portions of the first and third insulating patterns protrudes beyond a sidewall of the horizontal portion of the second insulating pattern in the second direction.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200135756A1

    公开(公告)日：2020-04-30

    申请号：US16425349

    申请日：2019-05-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joo-Heon KANG ,  Bongtae Park ,  Jae-Joo Shim

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/311 ,  H01L21/02

    Abstract: A 3D semiconductor memory device includes an electrode structure on a substrate, the electrode structure including gate electrodes stacked in a first direction perpendicular to a top surface of the substrate, a vertical semiconductor pattern penetrating the electrode structure and connected to the substrate, and a data storage pattern between the electrode structure and the vertical semiconductor pattern. The data storage pattern includes first, second and third insulating patterns sequentially stacked. Each of the first to third insulating patterns includes a horizontal portion extending in a second direction parallel to the top surface of the substrate. The horizontal portions of the first, second and third insulating patterns are sequentially stacked in the first direction. At least one of the horizontal portions of the first and third insulating patterns protrudes beyond a sidewall of the horizontal portion of the second insulating pattern in the second direction.

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