公开(公告)号：US20240260280A1

公开(公告)日：2024-08-01

申请号：US18457799

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngji NOH ,  Jongho WOO ,  Joo-Heon KANG ,  Myunghun WOO

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A semiconductor device including a cell array structure on a semiconductor substrate, the cell array structure including an electrode structure including electrodes and insulating layers vertically and alternately stacked on the semiconductor substrate, and a vertical structure and a penetration contact plug penetrating the electrode structure may be provided. The vertical structure may include a first inner layer, a first outer layer, and a first intermediate layer, and the penetration contact plug may include a second inner layer, a second outer layer, and a second intermediate layer. The electrodes may include a doped semiconductor material, and the first and second outer layers may include the same material. The first and second intermediate layers may include the same material, and the first and second inner layers may include materials different from each other.

公开(公告)号：US20240164116A1

公开(公告)日：2024-05-16

申请号：US18215280

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngji NOH ,  Jongho WOO ,  Joo-Heon KANG ,  Kyunghoon KIM ,  Myunghun WOO

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A semiconductor device includes a gate stacked structure including gate patterns and insulating patterns that are alternately stacked with each other; a gate insulating layer on a sidewall of the gate stacked structure; a channel layer surrounded by the gate insulating layer; a source line surrounded by the channel layer; a variable resistive layer surrounded by the channel layer; and a drain line surrounded by the channel layer.

公开(公告)号：US20220139954A1

公开(公告)日：2022-05-05

申请号：US17575947

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon KANG ,  Tae Hun KIM ,  Jae Ryong SIM ,  Kwang Young JUNG ,  Gi Yong CHUNG ,  Jee Hoon HAN ,  Doo Hee HWANG

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US20200135756A1

公开(公告)日：2020-04-30

申请号：US16425349

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Heon KANG ,  Bongtae Park ,  Jae-Joo Shim

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/311 ,  H01L21/02

Abstract: A 3D semiconductor memory device includes an electrode structure on a substrate, the electrode structure including gate electrodes stacked in a first direction perpendicular to a top surface of the substrate, a vertical semiconductor pattern penetrating the electrode structure and connected to the substrate, and a data storage pattern between the electrode structure and the vertical semiconductor pattern. The data storage pattern includes first, second and third insulating patterns sequentially stacked. Each of the first to third insulating patterns includes a horizontal portion extending in a second direction parallel to the top surface of the substrate. The horizontal portions of the first, second and third insulating patterns are sequentially stacked in the first direction. At least one of the horizontal portions of the first and third insulating patterns protrudes beyond a sidewall of the horizontal portion of the second insulating pattern in the second direction.