公开(公告)号：US20250107092A1

公开(公告)日：2025-03-27

申请号：US18972118

申请日：2024-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghun CHUN ,  Kwangyoung JUNG ,  Youngji NOH ,  Junghwan PARK ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

公开(公告)号：US20250159897A1

公开(公告)日：2025-05-15

申请号：US18667010

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngji NOH ,  Jongho WOO

IPC: H10B51/30 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B51/20 ,  H10B80/00

Abstract: A semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes stacked in a vertical direction; a plate layer on the stack structure; vertical structures respectively including a back gate electrode penetrating the stack structure and the plate layer in the vertical direction, a channel layer between the back gate electrode and the gate electrodes, and a gate dielectric structure including a ferroelectric layer between the channel layer and gate electrodes; a first horizontal insulating layer on upper surfaces of the plate layer and channel layer; a second horizontal insulating layer on the first horizontal insulating layer and including a material different than the first horizontal insulating layer; and back gate contacts on the respective vertical structures, connected to respective ones of the back gate electrodes, and including a pad region in the second horizontal insulating layer and a via region protruding upwardly from the pad region.

公开(公告)号：US20240164116A1

公开(公告)日：2024-05-16

申请号：US18215280

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngji NOH ,  Jongho WOO ,  Joo-Heon KANG ,  Kyunghoon KIM ,  Myunghun WOO

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A semiconductor device includes a gate stacked structure including gate patterns and insulating patterns that are alternately stacked with each other; a gate insulating layer on a sidewall of the gate stacked structure; a channel layer surrounded by the gate insulating layer; a source line surrounded by the channel layer; a variable resistive layer surrounded by the channel layer; and a drain line surrounded by the channel layer.

公开(公告)号：US20240260280A1

公开(公告)日：2024-08-01

申请号：US18457799

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngji NOH ,  Jongho WOO ,  Joo-Heon KANG ,  Myunghun WOO

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A semiconductor device including a cell array structure on a semiconductor substrate, the cell array structure including an electrode structure including electrodes and insulating layers vertically and alternately stacked on the semiconductor substrate, and a vertical structure and a penetration contact plug penetrating the electrode structure may be provided. The vertical structure may include a first inner layer, a first outer layer, and a first intermediate layer, and the penetration contact plug may include a second inner layer, a second outer layer, and a second intermediate layer. The electrodes may include a doped semiconductor material, and the first and second outer layers may include the same material. The first and second intermediate layers may include the same material, and the first and second inner layers may include materials different from each other.

公开(公告)号：US20230269942A1

公开(公告)日：2023-08-24

申请号：US18096257

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myunghun WOO ,  Jooheon KANG ,  Hyunmog PARK ,  Jongho WOO ,  Suseong NOH ,  Youngji NOH

IPC: H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/27 ,  H10B41/49 ,  H10B41/35

CPC classification number: H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/27 ,  H10B41/49 ,  H10B41/35

Abstract: A semiconductor device includes a gate stack structure including alternately stacked insulating patterns and conductive patterns; a memory channel structure extending through the gate stack structure; and a bit line pad on the memory channel structure, wherein the memory channel structure includes a variable resistance layer, a channel layer surrounding the variable resistance layer, and a channel insulating layer surrounding the channel layer, and a bottom surface of the bit line pad contacts a top surface of the variable resistance layer, a top surface of the channel layer, and a top surface of the channel insulating layer.

公开(公告)号：US20230005955A1

公开(公告)日：2023-01-05

申请号：US17742043

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun CHUN ,  Kwangyoung JUNG ,  Youngji NOH ,  Junghwan PARK ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.