公开(公告)号：US20240032298A1

公开(公告)日：2024-01-25

申请号：US18177335

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon PARK ,  Juseong MIN ,  Jaebok BAEK ,  Donghyuck JANG ,  Sanghun CHUN ,  Jeehoon HAN ,  Taeyoon HONG

IPC: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  G11C5/06

CPC classification number: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  G11C5/06

Abstract: A semiconductor device includes a peripheral circuit structure including circuits, wiring layers, and via contacts, a plate common source line covering the peripheral circuit structure, an insulating plug passing through the plate common source line, a lateral insulating spacer between the peripheral circuit structure and the plate common source line, a memory stack structure including gate lines on the plate common source line, a through contact passing through at least one of the gate lines and the insulating plug, the through contact being connected to a first via contact of the via contacts, and a source line contact passing through the lateral insulating spacer, the source line contact being between a second via contact of the via contacts and the plate common source line, wherein a width of the first via contact is greater than a width of the insulating plug in a lateral direction.

公开(公告)号：US20240130123A1

公开(公告)日：2024-04-18

申请号：US18208459

申请日：2023-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yejin PARK ,  Seung Yoon KIM ,  Heesuk KIM ,  Hyeongjin KIM ,  Sehee JANG ,  Minsoo SHIN ,  Seungjun SHIN ,  Sanghun CHUN ,  Jeehoon HAN ,  Jae-Hwang SIM ,  Jongseon AHN

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06541

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.

公开(公告)号：US20230005955A1

公开(公告)日：2023-01-05

申请号：US17742043

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun CHUN ,  Kwangyoung JUNG ,  Youngji NOH ,  Junghwan PARK ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

公开(公告)号：US20250107092A1

公开(公告)日：2025-03-27

申请号：US18972118

申请日：2024-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghun CHUN ,  Kwangyoung JUNG ,  Youngji NOH ,  Junghwan PARK ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

公开(公告)号：US20240090228A1

公开(公告)日：2024-03-14

申请号：US18300975

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoung CHOI ,  Sanghun CHUN ,  Jeehoon HAN

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device comprises a first substrate, a peripheral circuit structure, and a cell array structure including a cell array region and a cell array contact region. The cell array structure includes a second substrate, a stack structure including first and second stack structures, a vertical channel structure in the cell array region, and a cell contact plug in the cell array contact region. The cell contact plug includes a first pillar part and a first protrusion part. At the level of the top surface of the first protrusion part, a first width is given as a maximum diameter at an outer perimeter of the first protrusion part. At a level of an interface between the first and second stack structures, a second width is given as a maximum width of the vertical channel structure. The first width is greater than the second width.

公开(公告)号：US20240268113A1

公开(公告)日：2024-08-08

申请号：US18229560

申请日：2023-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun CHUN ,  Jaehoon LEE ,  Kyung Taek CHO ,  Donghyuck JANG ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a circuit region, a peripheral circuit structure on a first substrate; a cell region on the circuit region, a cell array region and connection region, the cell region including a second substrate; gate stacking structure on the second substrate, a lower structure, upper structures including gate electrodes; a channel structure penetrating the gate stacking structure; a gate contact penetrating the gate stacking structure electrically connected to the circuit region, and to a connection gate electrode insulated from a gate electrode by an insulating pattern between the gate electrode and the gate contact; a boundary insulating pattern partially formed in a boundary gate electrode among the gate electrodes of the lower structure adjacent to a boundary portion between the upper and lower structure surrounding the gate contact to maintain an electrical connection path of the boundary gate electrode and having a different structure from the insulating pattern.

公开(公告)号：US20240215252A1

公开(公告)日：2024-06-27

申请号：US18481404

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghun CHUN ,  Sehee JANG ,  Jeehoon HAN

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A nonvolatile memory device includes a peripheral circuit structure including a peripheral circuit and a first insulating structure covering the peripheral circuit and a cell array structure bonded to the peripheral circuit structure and including a cell region and a connection region, wherein the cell array structure includes a common source line layer, a buffer insulating layer on the common source line layer, a plurality of contact stop layers buried in the buffer insulating layer, a cell stack which includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on the buffer insulating layer, a plurality of cell channel structures extending to the common source line layer by passing through the cell stack, a plurality of contact structures each connected to one or more of the plurality of gate electrodes, and a second insulating structure covering the cell stack.

公开(公告)号：US20240063113A1

公开(公告)日：2024-02-22

申请号：US18192031

申请日：2023-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun CHUN ,  HOYOUNG CHOI ,  Haeli PARK ,  JEEHOON HAN

IPC: H01L23/522 ,  H10B43/27 ,  H10B41/27 ,  H10B80/00 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H10B43/27 ,  H10B41/27 ,  H10B80/00 ,  H01L21/76804 ,  H01L21/76829 ,  H10B41/10

Abstract: A semiconductor device including: a first gate stack including first insulating patterns and first conductive patterns; a second gate stack on the first gate stack, the second gate stack including second insulating patterns and second conductive patterns; a memory channel structure penetrating the first and second gate stacks; a penetration contact penetrating the first and second gate stacks; and a barrier pattern on opposite sides of the penetration contact, the first insulating patterns include a first connection insulating pattern, which is an uppermost one of the first insulating patterns, the second insulating patterns include a second connection insulating pattern which is in contact with a top surface of the first connection insulating pattern, a bottom surface of the barrier pattern is in contact with the top surface of the first connection insulating pattern, and a top surface of the barrier pattern is in contact with the second connection insulating pattern.

公开(公告)号：US20220336421A1

公开(公告)日：2022-10-20

申请号：US17582387

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon KIM ,  Junghoon JUN ,  Sanghun CHUN ,  Jeehoon HAN

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor memory device including a substrate, first pad layers and a second pad layer on the substrate, a pattern structure including first openings on the first pad layers and a second opening on the second pad layer, and having first and second regions, gate electrodes on the pattern structure and each including a pad region, channel structures penetrating through the gate electrodes in the first region, gate contact plugs electrically connected to the gate electrodes through the pad region of each of the gate electrodes and extending in a vertical direction to penetrate the first openings and connected to the first pad layers, a source contact plug, extending in the vertical direction penetrating the second opening and connected to the second pad layer, and a source connection patter under the pattern structure and in contact with the source contact plug and the second pad layer may be provided.