公开(公告)号：US20240260270A1

公开(公告)日：2024-08-01

申请号：US18508530

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoon HONG ,  Janggn YUN ,  Hyunho KIM ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

Abstract: A field effect transistor includes a horizontal channel layer, an interlayer insulating layer on the horizontal channel layer, a gate electrode layer on the interlayer insulating layer, a first vertical channel structure passing through the gate electrode layer and the interlayer insulating layer in a vertical direction, in contact with the horizontal channel layer, and connected to one of a source terminal or a drain terminal, and a second vertical channel structure apart from the first vertical channel structure in a horizontal direction, passing through the gate electrode layer and the interlayer insulating layer in the vertical direction, in contact with the horizontal channel layer, and connected to another of the source terminal or the drain terminal.

公开(公告)号：US20240113160A1

公开(公告)日：2024-04-04

申请号：US18303205

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juseong MIN ,  Kyeonghoon PARK ,  Jae-Bok BAEK ,  Donghyuck JANG ,  Jeehoon HAN ,  Taeyoon HONG

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/4236

Abstract: A semiconductor device include a substrate including a plurality of protrusions protruding from an upper surface thereof and arranged two-dimensionally in a first direction and a second direction intersecting each other, a first trench provided between the protrusions in the first direction, and a second trench provided between the protrusions in the second direction, a first device isolation layer filling the first trench, gate patterns disposed on the protrusions in the second direction, upper surfaces of the protrusions exposed at both sides of the gate patterns, respectively, and a second device isolation layer filling a space between the gate patterns in the second direction and the second trench, and each of the gate patterns has a first sidewall adjacent to the second trench and aligned with an inner wall of the second trench.

公开(公告)号：US20240032298A1

公开(公告)日：2024-01-25

申请号：US18177335

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon PARK ,  Juseong MIN ,  Jaebok BAEK ,  Donghyuck JANG ,  Sanghun CHUN ,  Jeehoon HAN ,  Taeyoon HONG

IPC: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  G11C5/06

CPC classification number: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  G11C5/06

Abstract: A semiconductor device includes a peripheral circuit structure including circuits, wiring layers, and via contacts, a plate common source line covering the peripheral circuit structure, an insulating plug passing through the plate common source line, a lateral insulating spacer between the peripheral circuit structure and the plate common source line, a memory stack structure including gate lines on the plate common source line, a through contact passing through at least one of the gate lines and the insulating plug, the through contact being connected to a first via contact of the via contacts, and a source line contact passing through the lateral insulating spacer, the source line contact being between a second via contact of the via contacts and the plate common source line, wherein a width of the first via contact is greater than a width of the insulating plug in a lateral direction.