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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210175173A1

    公开(公告)日：2021-06-10

    申请号：US17021321

    申请日：2020-09-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungjun SHIN ,  Siwan KIM ,  Bonghyun CHOI

    IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

    Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

    VERTICAL MEMORY DEVICES
    2.
    发明申请
    VERTICAL MEMORY DEVICES 有权

    公开(公告)号：US20240381641A1

    公开(公告)日：2024-11-14

    申请号：US18435342

    申请日：2024-02-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungeun PARK ,  Solmi KWAK ,  Jinhyuk KIM ,  Hyeongjin KIM ,  Jeongyong SUNG ,  Minsoo SHIN ,  Seungjun SHIN ,  Joongshik SHIN ,  Sunghee CHUNG ,  Jeehoon HAN

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

    Abstract: A vertical memory device may include a common source plate on a substrate including a first region and a second region; gate pattern structures on the common source plate and extending from the first region to the second region, wherein the gate pattern structures include gate patterns and first insulation layers, and wherein the adjacent gate pattern structures are spaced apart from each other; first separation patterns filling first openings between the adjacent gate pattern structures on the first region; second separation patterns filling second openings between the adjacent gate pattern structures on the second region, wherein at least one of the second separation patterns is connected to at least one of the first separation patterns, and wherein the second separation pattern has a shape different from a shape of the first separation pattern; and channel structures passing through the gate pattern structures on the first region.

    SEMICONDUCTOR DEVICE AND METHOD OF OPERATING AND CONTROLLING A SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF OPERATING AND CONTROLLING A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180053539A1

    公开(公告)日：2018-02-22

    申请号：US15649060

    申请日：2017-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungjun SHIN ,  Tae Young OH

    IPC: G11C7/22 ,  G11C7/18 ,  G11C8/10 ,  G11C7/12 ,  G11C7/06 ,  G11C8/08 ,  G11C8/14 ,  G11C7/10 ,  G11C7/20

    Abstract: An exemplary embodiment includes a method of controlling a semiconductor device. The semiconductor device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, a row decoder for receiving a row address and selecting a word line corresponding to the row address, a column decoder for receiving a column address and selecting a bit line corresponding to the column address, a sense amplifier for reading data stored in a memory cell connected to the selected word line and the selected bit line, and a data output driver. The method includes setting a calibration code for a driver control code, to control an initial current strength of the data output driver, and changing the calibration code to change the driver control code during a read or write operation for the memory cell array.

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230223346A1

    公开(公告)日：2023-07-13

    申请号：US18125177

    申请日：2023-03-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungjun SHIN ,  Siwan KIM ,  Bonghyun CHOI

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

    CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

    Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

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