公开(公告)号：US20200075605A1

公开(公告)日：2020-03-05

申请号：US16403795

申请日：2019-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Kwang-Soo KIM ,  Bonghyun CHOI ,  Siwan KIM

IPC: H01L27/115

Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

公开(公告)号：US20240064981A1

公开(公告)日：2024-02-22

申请号：US18386112

申请日：2023-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Seonho YOON ,  Bonghyun CHOI

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

公开(公告)号：US20230223346A1

公开(公告)日：2023-07-13

申请号：US18125177

申请日：2023-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun SHIN ,  Siwan KIM ,  Bonghyun CHOI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

公开(公告)号：US20220123019A1

公开(公告)日：2022-04-21

申请号：US17567364

申请日：2022-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Seonho YOON ,  Bonghyun CHOI

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

公开(公告)号：US20210175173A1

公开(公告)日：2021-06-10

申请号：US17021321

申请日：2020-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun SHIN ,  Siwan KIM ,  Bonghyun CHOI

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

公开(公告)号：US20210043648A1

公开(公告)日：2021-02-11

申请号：US16850097

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Seonho YOON ,  Bonghyun CHOI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.