公开(公告)号：US20220336489A1

公开(公告)日：2022-10-20

申请号：US17529331

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seugmin LEE ,  Kiyoon KANG ,  Kangmin KIM ,  Dongseong KIM ,  Junhyoung KIM ,  Byungkwan YOU

IPC: H01L27/11582 ,  H01L23/00

Abstract: A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure disposed on the source structure and including insulating patterns and conductive patterns alternately stacked, a memory channel structure electrically connected to the source structure and penetrating the gate stack structure, a support structure penetrating the gate stack structure and the source structure, and an insulating layer covering the gate stack structure, the memory channel structure and the support structure. The support structure includes an outer support layer contacting side walls of the insulating patterns and side walls of the conductive patterns, and a support pattern and an inner support layer contacting an inner side wall of the outer support layer.

公开(公告)号：US20220173120A1

公开(公告)日：2022-06-02

申请号：US17465412

申请日：2021-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin LEE ,  Junhyoung KIM ,  Kangmin KIM ,  Byungkwan YOU

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes: a substrate that includes a first region and a second region; gate electrodes stacked on the first region in a first direction, extend by different lengths in a second direction on the second region, and respectively including a pad region having an upper surface that is upwardly exposed in the second region; interlayer insulating layers alternately stacked with the gate electrodes; channel structures that extend in the first direction and penetrate through the gate electrodes; plug insulating layers alternately disposed with the interlayer insulating layers and parallel to the gate electrodes below the pad region; and contact plugs that extend in the first direction and respectively penetrate through the pad region and the plug insulating layers below the pad region. In each of the gate electrodes, the pad region has physical properties that differ from physical properties of regions other than the pad region.

公开(公告)号：US20220123019A1

公开(公告)日：2022-04-21

申请号：US17567364

申请日：2022-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Seonho YOON ,  Bonghyun CHOI

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

公开(公告)号：US20240224514A1

公开(公告)日：2024-07-04

申请号：US18498673

申请日：2023-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Jimo GU ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H10B41/27 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B41/27 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: An integrated circuit device includes a substrate including a memory cell area and a connection area, a gate stack including a plurality of gate electrodes apart from each other in a vertical direction on the substrate, a plurality of gate connection openings arranged in the connection area to extend inward from an upper surface of the gate stack, one of the plurality of gate electrodes being exposed at a bottom surface of each of the plurality of gate connection openings, a plurality of gate connection structures respectively covering at least inner side surfaces of the plurality of gate connection openings, each of the plurality of gate connection structures being connected with the one gate electrode, and a plurality of gate contacts respectively connected to upper ends of the plurality of gate connection structures.

公开(公告)号：US20240203943A1

公开(公告)日：2024-06-20

申请号：US18346921

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Jiwon KIM ,  Minyong LEE ,  Dohyung KIM ,  Sukkang SUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/528 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/80379 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: The inventive concept provides a chip stack structure including a first semiconductor chip and a second semiconductor chip bonded to each other, and a semiconductor package including a plurality of chip stack structures stacked in a vertical direction.

公开(公告)号：US20220344267A1

公开(公告)日：2022-10-27

申请号：US17861700

申请日：2022-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Joongshik SHIN ,  Kwangsoo KIM

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.

公开(公告)号：US20200075605A1

公开(公告)日：2020-03-05

申请号：US16403795

申请日：2019-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Kwang-Soo KIM ,  Bonghyun CHOI ,  Siwan KIM

IPC: H01L27/115

Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

公开(公告)号：US20240064981A1

公开(公告)日：2024-02-22

申请号：US18386112

申请日：2023-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Seonho YOON ,  Bonghyun CHOI

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

公开(公告)号：US20230247829A1

公开(公告)日：2023-08-03

申请号：US18132019

申请日：2023-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Jisung CHEON

IPC: H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.

公开(公告)号：US20230232632A1

公开(公告)日：2023-07-20

申请号：US18188946

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Geunwon Lim ,  Manjoong Kim

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.