公开(公告)号：US20230005955A1

公开(公告)日：2023-01-05

申请号：US17742043

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun CHUN ,  Kwangyoung JUNG ,  Youngji NOH ,  Junghwan PARK ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

公开(公告)号：US20220102369A1

公开(公告)日：2022-03-31

申请号：US17318306

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong CHUNG ,  Jaeryong SIM ,  Kwangyoung JUNG ,  Jeehoon HAN

IPC: H01L27/11575 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

公开(公告)号：US20250056808A1

公开(公告)日：2025-02-13

申请号：US18931606

申请日：2024-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong CHUNG ,  Jaeryong SIM ,  Kwangyoung JUNG ,  Jeehoon HAN

IPC: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

公开(公告)号：US20250107092A1

公开(公告)日：2025-03-27

申请号：US18972118

申请日：2024-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghun CHUN ,  Kwangyoung JUNG ,  Youngji NOH ,  Junghwan PARK ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

公开(公告)号：US20250106975A1

公开(公告)日：2025-03-27

申请号：US18738968

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon PARK ,  Kwangyoung JUNG ,  Seunghun KIM ,  Jung-Soon BOK ,  Jiho UH ,  Hyunjoon OHN ,  WonHee YOON

IPC: H05H1/24 ,  G01K7/00

Abstract: Provided is a plasma generating system including: a resonant inverter including a switching circuit and configured to generate a device output current and a device output voltage, and to have a switching frequency based on an input DC current and an input DC voltage; a plasma source configured to generate a plasma based on the device output current and the device output voltage; a controller configured to control the switching frequency of the resonant inverter based on a value of the input DC current, a value of the input DC voltage, a value of the device output current, and a value of the device output voltage; and a junction temperature estimator configured to: estimate a current output from the switching circuit based on the value of the input DC voltage, the value of the device output current, and the value of the device output voltage, generate an inverted current estimate value, and estimate a junction temperature of the switching circuit based on the inverted current estimate value.

公开(公告)号：US20220139945A1

公开(公告)日：2022-05-05

申请号：US17357213

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung JUNG ,  Jaebok BAEK ,  Giyong CHUNG ,  Jeehoon HAN

IPC: H01L27/11565 ,  H01L25/18 ,  H01L25/065 ,  H01L27/11582

Abstract: A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.

公开(公告)号：US20210384210A1

公开(公告)日：2021-12-09

申请号：US17155225

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyoun JO ,  Kohji KANAMORI ,  Kwangyoung JUNG ,  Jeehoon HAN

IPC: H01L27/11556 ,  H01L23/528 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519

Abstract: A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.