公开(公告)号：US20240090228A1

公开(公告)日：2024-03-14

申请号：US18300975

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoung CHOI ,  Sanghun CHUN ,  Jeehoon HAN

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device comprises a first substrate, a peripheral circuit structure, and a cell array structure including a cell array region and a cell array contact region. The cell array structure includes a second substrate, a stack structure including first and second stack structures, a vertical channel structure in the cell array region, and a cell contact plug in the cell array contact region. The cell contact plug includes a first pillar part and a first protrusion part. At the level of the top surface of the first protrusion part, a first width is given as a maximum diameter at an outer perimeter of the first protrusion part. At a level of an interface between the first and second stack structures, a second width is given as a maximum width of the vertical channel structure. The first width is greater than the second width.