公开(公告)号：US11495615B2

公开(公告)日：2022-11-08

申请号：US17009075

申请日：2020-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungeun Park ,  Jae-Joo Shim ,  Dongsung Woo ,  Jongkwang Lim ,  Jaehoon Jang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11539 ,  H01L27/11565

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.