公开(公告)号：US11062784B2

公开(公告)日：2021-07-13

申请号：US16844317

申请日：2020-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US10037888B2

公开(公告)日：2018-07-31

申请号：US15093933

申请日：2016-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungkeun Son ,  Hansoo Kim ,  Jinho Kim ,  Kihyun Kim

IPC: H01L29/788 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/11582 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11553 ,  H01L27/11519

CPC classification number: H01L21/28 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7841 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/7889

Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

公开(公告)号：US20240155840A1

公开(公告)日：2024-05-09

申请号：US18416095

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H10B43/27 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/408 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L2924/0002

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US11715537B2

公开(公告)日：2023-08-01

申请号：US17542183

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/34 ,  G11C16/04 ,  H10B43/27 ,  G11C16/08 ,  G11C16/12 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  H10B43/35

CPC classification number: G11C16/3459 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H10B43/27 ,  H10B43/35

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20220037355A1

公开(公告)日：2022-02-03

申请号：US17497417

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US10650903B2

公开(公告)日：2020-05-12

申请号：US16206383

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US10546872B2

公开(公告)日：2020-01-28

申请号：US15634597

申请日：2017-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US09735170B2

公开(公告)日：2017-08-15

申请号：US14973182

申请日：2015-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L29/788 ,  H01L27/11582 ,  H01L27/11578 ,  H01L23/498 ,  H01L27/11575 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/408 ,  H01L29/4234 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US09490130B2

公开(公告)日：2016-11-08

申请号：US14726648

申请日：2015-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong In Yun ,  Jin-Soo Lim ,  Hansoo Kim ,  Sung-Hwan Jang ,  Youngwoo Park ,  Byoungkeun Son

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/311

CPC classification number: H01L29/78 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.

Abstract translation: 一种制造三维半导体存储器件的方法包括通过在衬底上交替地堆叠第一和第二材料层来形成薄层结构，形成穿透薄层结构的穿透凹陷，并使基底凹陷的顶部表面露出 形成穿透薄层结构的垂直绝缘层以覆盖穿透凹陷的内壁，形成穿透穿孔凹陷处的垂直绝缘层的半导体图案，以插入到基板中，并且在薄的层间形成氧化物层 通过氧化渗透凹陷的侧壁来形成层状结构和基底。

公开(公告)号：US09418911B2

公开(公告)日：2016-08-16

申请号：US14925789

申请日：2015-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Joo Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

IPC: H01L23/52 ,  H01L23/31 ,  H01L27/115 ,  H01L21/768 ,  H01L23/29 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract translation: 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括布置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。