公开(公告)号：US12082412B2

公开(公告)日：2024-09-03

申请号：US17154159

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Young Lim ,  Jongsoo Kim ,  Jesuk Moon ,  Dongwoo Kim ,  Sunil Shim ,  Wonseok Cho

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.

公开(公告)号：US11943926B2

公开(公告)日：2024-03-26

申请号：US17377869

申请日：2021-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonseok Cho ,  Seulbi Lee

IPC: H10B43/30 ,  H01L21/762 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L23/00

CPC classification number: H10B43/27 ,  H01L21/76232 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H01L24/08 ,  H01L2224/08145

Abstract: A semiconductor device including a substrate; a horizontal conductive layer disposed on the substrate; a support layer disposed on the horizontal conductive layer; a stack structure including a plurality of gate electrodes, stacked to be spaced apart from each other in a direction perpendicular to an upper surface of the support layer, and a plurality of interlayer insulating layers stacked alternately with the plurality of gate electrodes; a channel structure penetrating through the stack structure; a separation structure penetrating through the horizontal conductive layer, the support layer, and the stack structure and extending in a first direction; and a conductive pattern disposed on a level between the horizontal conductive layer and a lowermost interlayer insulating layer, among the plurality of interlayer insulating layers, and protruding outwardly of the separation structure from a side surface of the separation structure.

公开(公告)号：US11295815B2

公开(公告)日：2022-04-05

申请号：US16781986

申请日：2020-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyong Kim ,  Sunil Shim ,  Wonseok Cho

IPC: G11C16/08 ,  G11C16/04

Abstract: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.

公开(公告)号：US09698155B2

公开(公告)日：2017-07-04

申请号：US14563432

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil Shim ,  Wonseok Cho ,  Woonkyung Lee

IPC: H01L27/115 ,  H01L27/24 ,  H01L27/11582 ,  H01L29/78 ,  H01L23/538 ,  H01L27/11565 ,  H01L27/11556 ,  H01L45/00

CPC classification number: H01L27/11582 ,  H01L23/5384 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/2409 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/7827 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.

公开(公告)号：US12125535B2

公开(公告)日：2024-10-22

申请号：US17698627

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyong Kim ,  Sunil Shim ,  Wonseok Cho

IPC: G11C16/08 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0466 ,  G11C16/0483

Abstract: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.

公开(公告)号：US11637117B2

公开(公告)日：2023-04-25

申请号：US17032277

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Kwanyong Kim ,  Seogoo Kang ,  Sunil Shim ,  Wonseok Cho ,  Jeehon Han

IPC: H01L27/1157 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor device includes; a memory stack disposed on a substrate and including a lower gate electrode, an upper gate stack including a string selection line, a vertically extending memory gate contact disposed on the lower gate electrode, and a vertically extending selection line stud disposed on the string selection line. The string selection line includes a material different from that of the lower gate electrode, and the selection line stud includes a material different from that of the memory gate contact.

公开(公告)号：US09418911B2

公开(公告)日：2016-08-16

申请号：US14925789

申请日：2015-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Joo Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

IPC: H01L23/52 ,  H01L23/31 ,  H01L27/115 ,  H01L21/768 ,  H01L23/29 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract translation: 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括布置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

公开(公告)号：US09196525B2

公开(公告)日：2015-11-24

申请号：US14276124

申请日：2014-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Joo Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

IPC: H01L21/768 ,  H01L27/115

CPC classification number: H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract translation: 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括布置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

公开(公告)号：US20140248766A1

公开(公告)日：2014-09-04

申请号：US14276124

申请日：2014-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-JOO SHIM ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

IPC: H01L21/768

CPC classification number: H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract translation: 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括设置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

公开(公告)号：US10903227B2

公开(公告)日：2021-01-26

申请号：US15609578

申请日：2017-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil Shim ,  Wonseok Cho ,  Woonkyung Lee

IPC: H01L27/11582 ,  H01L29/78 ,  H01L23/538 ,  H01L27/24 ,  H01L27/11565 ,  H01L27/11556 ,  H01L45/00

Abstract: A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.