公开(公告)号：US20200105785A1

公开(公告)日：2020-04-02

申请号：US16392958

申请日：2019-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAE-CHUL JUNG ,  BONG-TAE PARK ,  JAE-JOO SHIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/528

Abstract: A vertical semiconductor device includes a substrate with a first and second region. A conductive pattern on the first region extends in a first direction. The first region includes a cell region, a first dummy region and a second dummy region. The conductive pattern extends in a first direction. A pad is disposed on the second region, the pad contacts a side of the conductive pattern. A plurality of first dummy structures extends through the conductive pattern on the first dummy region. A plurality of second dummy structures extend through the conductive pattern on the second dummy region, the second dummy structures disposed in a plurality of columns that extend in a second direction perpendicular to the first direction. Widths of upper surfaces of the second dummy structures are different in each column, and the widths of upper surfaces of the second dummy structures increase toward the second region.

公开(公告)号：US20160049346A1

公开(公告)日：2016-02-18

申请号：US14925789

申请日：2015-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-JOO SHIM ,  HANSOO KIM ,  WONSEOK CHO ,  JAEHOON JANG ,  WOOJIN CHO

IPC: H01L23/31 ,  H01L23/29 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract translation: 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括布置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

公开(公告)号：US20140248766A1

公开(公告)日：2014-09-04

申请号：US14276124

申请日：2014-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-JOO SHIM ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

IPC: H01L21/768

CPC classification number: H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract translation: 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括设置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。