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1.发明授权公开(公告)号：US12105137B2
公开(公告)日：2024-10-01
申请号：US17360573
申请日：2021-06-28
IPC分类号： G01R31/27 , G01R31/317 , G01R31/3181 , G01R31/3183 , G06N3/063
CPC分类号： G01R31/275 , G01R31/31707 , G01R31/31813 , G01R31/31835 , G06N3/063
摘要： To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.
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公开(公告)号：US11871580B2
公开(公告)日：2024-01-09
申请号：US17317479
申请日：2021-05-11
发明人： Peng Zhang , Yanli Zhang , Xiang Yang , Koichi Matsuno , Masaaki Higashitani , Johann Alsmeier
IPC分类号： H10B51/30 , H01L21/764 , H01L29/06 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B51/20
CPC分类号： H10B51/30 , H01L21/764 , H01L29/0649 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B51/20
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.
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公开(公告)号：US20230367944A1
公开(公告)日：2023-11-16
申请号：US17740705
申请日：2022-05-10
发明人： Yuki Mizutani , Masaaki Higashitani
IPC分类号： G06F30/392 , G06F30/394 , H03K19/0185
CPC分类号： G06F30/392 , G06F30/394 , H03K19/018521
摘要： The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.
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公开(公告)号：US11676954B2
公开(公告)日：2023-06-13
申请号：US17134997
申请日：2020-12-28
发明人： Peter Rabkin , Masaaki Higashitani , Kwang-ho Kim
IPC分类号： H01L25/065 , H01L23/528 , H01L25/18 , H01L23/00 , H01L25/00 , H10B41/27 , H10B43/27
CPC分类号： H01L25/18 , H01L23/5286 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/50 , H10B41/27 , H10B43/27 , H01L2224/08145 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers; memory openings extending through the alternating stack, memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, a source layer contacting the vertical semiconductor channels, a backside isolation dielectric layer contacting a backside surface of the source layer, and a source power supply mesh including a planar portion of a source-side electrically conductive layer that is located on a backside of the backside isolation dielectric layer and electrically connected to the source layer by conductive material portions that extend through the backside isolation dielectric layer.
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5.发明公开公开(公告)号：US20230142936A1
公开(公告)日：2023-05-11
申请号：US18152669
申请日：2023-01-10
CPC分类号： G06T7/0002 , G06N20/20
摘要： To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.
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6.发明申请公开(公告)号：US20230054342A1
公开(公告)日：2023-02-23
申请号：US17979142
申请日：2022-11-02
IPC分类号： G05B19/418
摘要： To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.
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7.发明授权公开(公告)号：US11569259B2
公开(公告)日：2023-01-31
申请号：US16985305
申请日：2020-08-05
发明人： Yuki Mizutani , Masaaki Higashitani
IPC分类号： H01L27/11582 , H01L23/528 , H01L27/11565 , H01L23/522 , H01L27/1157
摘要： A memory die can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures vertically extending through the alternating stack. A first layer stack within the alternating stack includes a first staircase region in which the first electrically conductive layers have respective lateral extents that increase with a vertical distance from the substrate to provide first stepped surfaces. A second layer stack within the alternating stack includes a second staircase region in which the second electrically conductive layers have respective lateral extents that decrease with the vertical distance from the substrate to provide second stepped surfaces. The second layer stack can be more distal from the substrate than the first layer stack. Contact via structures can be formed from the top side and the bottom side of the alternating stack.
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公开(公告)号：US20220415718A1
公开(公告)日：2022-12-29
申请号：US17725695
申请日：2022-04-21
发明人： Cheng-Chung Chu , Masaaki Higashitani , Yusuke Ikawa , Seyyed Ehsan Esfahani Rashidi , Kei Samura , Tsuyoshi Sendoda , Yanli Zhang
IPC分类号： H01L21/66 , H01L27/11578
摘要： To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.
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9.发明授权公开(公告)号：US11508654B2
公开(公告)日：2022-11-22
申请号：US16886702
申请日：2020-05-28
IPC分类号： H01L23/522 , H01L23/528 , H01L27/115 , H01L27/06 , H01L23/00 , H01L49/02 , H01L27/11582
摘要： A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
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10.发明授权公开(公告)号：US11387142B1
公开(公告)日：2022-07-12
申请号：US17208019
申请日：2021-03-22
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L27/11556 , H01L27/11582 , H01L27/11573 , H01L27/11529
摘要： A semiconductor structure includes a semiconductor device, bit lines electrically connected to the semiconductor device, air gaps located between the bit lines, a capping-level material layer, a via-level dielectric material layer located between the bit lines and the capping-level material layer, and conductive via structures extending through the via-level dielectric material layer and contacting a top surface of a respective one of the bit lines. The capping-level material layer contains cavity-containing openings exposing the air gaps. The capping-level material layer contains protruding portions that extend into peripheral regions of the cavity-containing openings.
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