公开(公告)号：US09818829B2

公开(公告)日：2017-11-14

申请号：US15214335

申请日：2016-07-19

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yeeheng Lee ,  Sik Lui ,  Jongoh Kim ,  Hong Chang ,  Madhur Bobde ,  Lingpeng Guan ,  Hamza Yilmaz

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L27/02

CPC分类号： H01L29/407 ,  H01L21/28008 ,  H01L21/28114 ,  H01L27/0255 ,  H01L27/0266 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827

摘要： Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US09356132B2

公开(公告)日：2016-05-31

申请号：US14318408

申请日：2014-06-27

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Hong Chang ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/872 ,  H01L29/40 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L29/47 ,  H01L29/49 ,  H01L29/06

CPC分类号： H01L29/7801 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0891 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/872

摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

公开(公告)号：US20150380544A1

公开(公告)日：2015-12-31

申请号：US14845128

申请日：2015-09-03

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Hong Chang ,  Yeeheng Lee ,  Daniel Calafut ,  Jongoh Kim ,  Sik Lui ,  John Chen

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L27/02 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L27/0251 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7827

摘要： Aspects of the present disclosure describe a high density trench-based power. The active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. A lightly doped sub-body layer may be formed below a body region between two or more adjacent active device structures of the plurality. The sub-body layer extends from a depth of the upper portion of the gate oxide to a depth of the lower portion of the gate oxide It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了高密度基于沟槽的功率。 有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 轻掺杂子体层可以形成在多个相邻的有源器件结构之间的体区之下。 子体层从栅极氧化物的上部的深度延伸到栅极氧化物的下部的深度。强调该抽象被提供以符合要求抽象的规则，其将允许搜索者或其他 读者快速确定技术披露的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20150372129A1

公开(公告)日：2015-12-24

申请号：US14841491

申请日：2015-08-31

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type. A first conductivity type epitaxial layer disposed on a top surface of the substrate includes a surface shielded region above a less heavily doped voltage blocking region. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the surface shielded region. A first conductivity type source region is disposed near the top surface inside the body region. A drain is disposed at a bottom surface of the substrate. A gate overlaps portions of the source and body regions. Gate insulation separates the gate from the source and body regions. First and second trenches formed in the surface shielded region are lined with trench insulation material and filled with electrically conductive trench filling material. Second conductivity type buried doped regions are positioned below the first and second trenches, respectively.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底。 设置在衬底的顶表面上的第一导电类型外延层包括在较低重掺杂的电压阻挡区域之上的表面屏蔽区域。 与第一导电类型相反的第二导电类型的主体区域设置在表面屏蔽区域的顶表面附近。 第一导电型源区域设置在身体区域内的顶表面附近。 漏极设置在衬底的底表面。 门与源区和身体区的部分重叠。 门绝缘将门与源区和身体区分开。 形成在表面屏蔽区域中的第一和第二沟槽衬有沟槽绝缘材料，并填充有导电沟槽填充材料。 第二导电型掩埋掺杂区分别位于第一和第二沟槽的下方。

公开(公告)号：US20150333174A1

公开(公告)日：2015-11-19

申请号：US14807633

申请日：2015-07-23

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yeeheng Lee ,  Madhur Bobde ,  Daniel Calafut ,  Hamza Yilmaz ,  Xiaobin Wang ,  Ji Pan ,  Hong Chang ,  Jongoh Kim

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  H01L29/40 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L29/66143 ,  H01L21/265 ,  H01L21/308 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66257 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/872

摘要： A semiconductor device may have an active device region containing a plurality of active devices and a termination structure that surrounds the active device region. The termination structure includes a first conductive region that surrounds the active device region, an insulator region that surrounds the first conductive region, and a second conductive region that surrounds the first conductive region and the insulator region. The active device region and termination structure are formed into a semiconductor material of a first conductivity type. The first conductive region is electrically connected to a gate metal and the second conductive region is connected to a drain metal.

摘要翻译： 半导体器件可以具有包含多个有源器件的活动器件区域和围绕有源器件区域的端接结构。 端接结构包括围绕有源器件区的第一导电区域，围绕第一导电区域的绝缘体区域和围绕第一导电区域和绝缘体区域的第二导电区域。 有源器件区域和端接结构形成为第一导电类型的半导体材料。 第一导电区域电连接到栅极金属，并且第二导电区域连接到漏极金属。

公开(公告)号：US20150194522A1

公开(公告)日：2015-07-09

申请号：US14660361

申请日：2015-03-17

申请人： ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/78 ,  H01L29/40

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

摘要翻译： 一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。 沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。 使用第二掩模形成由中间介电区分隔的第一和第二导电区域。 使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。 使用第四掩模形成与栅极金属区域的接触。 半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

公开(公告)号：US08809948B1

公开(公告)日：2014-08-19

申请号：US13724180

申请日：2012-12-21

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Hong Chang ,  Yeeheng Lee ,  Daniel Calafut ,  Jongoh Kim ,  Sik Lui ,  John Chen

IPC分类号： H01L29/66 ,  H01L29/76 ,  H01L27/12 ,  H01L27/088 ,  H01L21/336 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L27/0251 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7827

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。 源触点与沿着栅极盖的侧壁形成的间隔物自对准。 另外，有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 与自对准源触点结合的两步栅极氧化物允许生产具有深亚微米级的间距的器件。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20140073098A1

公开(公告)日：2014-03-13

申请号：US14083309

申请日：2013-11-18

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Daniel Calafut ,  Yi Su ,  Jongoh Kim ,  Hong Chang ,  Hamza Yilmaz ,  Daniel S. Ng

IPC分类号： H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/06 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/872

摘要： A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches to fill the remaining portions of the first and second trenches; and forming a Schottky metal layer on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction. The Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode.

摘要翻译： 一种用于形成肖特基二极管的方法，包括在半导体层中形成第一和第二沟槽，形成衬在第一和第二沟槽的侧壁上的薄介电层; 在所述第一和第二沟槽中形成沟槽导体层，其中所述沟槽导体层填充所述第一和第二沟槽中的每一个的一部分，并且是所述第一和第二沟槽中唯一的一个沟槽导体层; 在所述第一和第二沟槽中形成第一介电层以填充所述第一和第二沟槽的剩余部分; 以及在所述第一沟槽和所述第二沟槽之间的所述轻掺杂半导体层的顶表面上形成肖特基金属层以形成肖特基结。 肖特基二极管由肖特基金属层作为阳极形成，而第一和第二沟槽之间的轻掺杂半导体层作为阴极形成。

公开(公告)号：US10115814B2

公开(公告)日：2018-10-30

申请号：US15875932

申请日：2018-01-19

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yongping Ding ,  Lei Zhang ,  Hong Chang ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/265

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

公开(公告)号：US09484452B2

公开(公告)日：2016-11-01

申请号：US14565668

申请日：2014-12-10

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Sik Lui ,  Hamza Yilmaz ,  Jongoh Kim ,  Daniel Ng

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40 ,  H01L29/36

CPC分类号： H01L29/66734 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66492 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L29/8725

摘要： A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate. A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 μm to 0.2 μm.

摘要翻译： 多个栅极沟槽在半导体衬底上形成为第一导电类型的外延区域。 一个或多个接触沟槽形成到外延区域中，每个在两个相邻的栅极沟槽之间。 第一导电类型的一个或多个源极区域形成在接触沟槽和栅极沟槽之间的外延区域的顶部。 在每个接触沟槽内形成阻挡金属。 每个栅极沟槽基本上填充有通过介电材料层与沟槽壁分离以形成栅极的导电材料。 在靠近每个接触沟槽的底部的外延区域中提供了与第一类型相反的导电性的重掺杂阱区。 阱区和栅极沟槽之间的间隙的水平宽度为约0.05μm至0.2μm。