公开(公告)号：US20180226513A1

公开(公告)日：2018-08-09

申请号：US15947010

申请日：2018-04-06

申请人： United Silicon Carbide, Inc.

发明人： Zhongda Li ,  Anup Bhalla

IPC分类号： H01L29/808 ,  H01L29/66 ,  H01L21/02 ,  H01L29/45 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L21/768 ,  H01L21/04

CPC分类号： H01L29/8083 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/045 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/76897 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66909

摘要： A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

公开(公告)号：US20180212045A1

公开(公告)日：2018-07-26

申请号：US15681597

申请日：2017-08-21

申请人： Qorvo US, Inc.

发明人： Jinqiao Xie ,  Xing Gu ,  Edward A. Beam, III

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66909 ,  H01L21/02389 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02647 ,  H01L27/14679 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66734 ,  H01L29/66893 ,  H01L29/66924 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/8086 ,  H01L2924/13062

摘要： A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

公开(公告)号：US20170213917A1

公开(公告)日：2017-07-27

申请号：US15482139

申请日：2017-04-07

申请人： United Silicon Carbide, Inc.

发明人： Anup Bhalla ,  Zhongda Li

IPC分类号： H01L29/808 ,  H01L29/10 ,  H01L21/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/16 ,  H01L29/08

CPC分类号： H01L29/8083 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66909

摘要： A JFET having vertical and horizontal channel elements may be made from a semiconductor material such as silicon carbide using a first mask for multiple implantations to form a horizontal planar JFET region comprising a lower gate, a horizontal channel, and an upper gate, all above a drift region resting on a drain substrate region, such that the gates and horizontal channel are self-aligned with the same outer size and outer shape in plan view. A second mask may be used to create a vertical channel region abutting the horizontal channel region. The horizontal channel and vertical channel may each have multiple layers with varying doping concentrations. Angled implantations may use through the first mask to implant portions of the vertical channel regions. The window of the second mask may partially overlap the horizontal JFET region to insure abutment of the vertical and horizontal channel regions.

公开(公告)号：US09653585B2

公开(公告)日：2017-05-16

申请号：US15177231

申请日：2016-06-08

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L31/0328 ,  H01L21/00 ,  H01L21/337 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/775 ,  H01L27/08 ,  H01L29/49 ,  H01L21/8238

CPC分类号： H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

摘要： A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US20170117392A1

公开(公告)日：2017-04-27

申请号：US15267177

申请日：2016-09-16

申请人： United Silicon Carbide, Inc.

发明人： Anup Bhalla ,  Zhongda Li

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/8083 ,  H01L21/0465 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66909

摘要： A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.

公开(公告)号：US09608092B2

公开(公告)日：2017-03-28

申请号：US14822267

申请日：2015-08-10

申请人： Infineon Technologies AG

发明人： Jens Konrath ,  Hans-Joachim Schulze ,  Roland Rupp ,  Wolfgang Werner ,  Frank Pfirsch

IPC分类号： H01L29/80 ,  H01L29/66 ,  H01L29/78 ,  H01L29/47 ,  H01L29/04 ,  H01L29/16 ,  H01L29/812 ,  H01L29/267 ,  H01L29/872

CPC分类号： H01L29/66909 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/8122 ,  H01L29/872

摘要： A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches.

公开(公告)号：US20170040312A1

公开(公告)日：2017-02-09

申请号：US14817835

申请日：2015-08-04

申请人： Infineon Technologies Austria AG

发明人： Gilberto Curatola ,  Ralf Siemieniec

IPC分类号： H01L27/06 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/84 ,  H01L21/8258 ,  H01L29/872 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L29/16 ,  H01L29/10 ,  H01L29/808

CPC分类号： H01L27/0629 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/76898 ,  H01L21/8258 ,  H01L27/0617 ,  H01L27/0688 ,  H01L27/0727 ,  H01L27/085 ,  H01L29/0646 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66143 ,  H01L29/66462 ,  H01L29/66909 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/8083 ,  H01L29/84 ,  H01L29/872

摘要： A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region.

摘要翻译： 半导体器件包括包括第一和第二侧表面的半导体本体。 第一器件区域包括第一导电类型的漂移区，并且第二导电类型的漂移电流控制区域与漂移区域与第二侧表面间隔开。 第二器件区域包括阻挡层和与阻挡层具有不同带隙的缓冲层，使得沿着缓冲层和阻挡层之间的界面产生二维电荷载流子通道。 导电衬底接触在二维电荷载气通道和漂移区之间形成低欧姆连接。 门结构被配置为控制二维电荷载气的导通状态。 漂移电流控制区被配置为通过空间电荷区域来阻挡漂移区中的垂直电流。

公开(公告)号：US20170018657A1

公开(公告)日：2017-01-19

申请号：US14798631

申请日：2015-07-14

申请人： United Silicon Carbide, Inc.

发明人： Zhongda Li ,  Anup Bhalla

IPC分类号： H01L29/808 ,  H01L29/66 ,  H01L21/04 ,  H01L29/06 ,  H01L21/02 ,  H01L29/16 ,  H01L29/45

CPC分类号： H01L29/8083 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/045 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/76897 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66909

摘要： A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

摘要翻译： 使用有限数量的掩模的工艺制成的垂直JFET。 第一掩模用于同时在活性细胞和终止区域中形成台面和沟槽。 使用无掩模自对准工艺来形成硅化物源极和栅极接触。 第二个掩码用于打开窗口到联系人。 第三个掩模用于图案覆盖金属化。 使用可选的第四个掩模来图案化钝化。 可选地，可以通过成角度的注入来掺杂沟道，并且活性单元区域中的沟槽和台面的宽度可以与端接区域中的那些不同。

公开(公告)号：US09543395B2

公开(公告)日：2017-01-10

申请号：US14536625

申请日：2014-11-09

申请人： Renesas Electronics Corporation

发明人： Koichi Arai ,  Yasuaki Kagotoshi ,  Nobuo Machida ,  Natsuki Yokoyama ,  Haruka Shimizu

IPC分类号： H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/808

CPC分类号： H01L29/36 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66909 ,  H01L29/8083

摘要： In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

摘要翻译： 通常，在诸如基于SiC的正常关断JFET的半导体有源元件中，其中杂质扩散速度显着低于硅中的杂质扩散速度，通过离子注入形成在源区中形成的沟槽的侧壁中形成栅极区。 然而，为了确保JFET的性能，需要高精度地控制栅极区域之间的面积。 此外，存在这样的问题，由于通过在源极区域中形成栅极区域而形成重掺杂的PN结，所以不能避免结电流的增加。 本发明提供一种常闭功率JFET及其制造方法，根据多次外延法形成栅极区域，该方法重复包括外延生长，离子注入和激活退火多次的工艺。

公开(公告)号：US20160293602A1

公开(公告)日：2016-10-06

申请号：US14677404

申请日：2015-04-02

申请人： STMicroelectronics, Inc.

发明人： Qing Liu ,  John Hongguang Zhang

IPC分类号： H01L27/098 ,  H01L29/808 ,  H01L21/283 ,  H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66893 ,  H01L21/283 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66909 ,  H01L29/7832 ,  H01L29/8083

摘要： A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

摘要翻译： 垂直结型场效应晶体管（JFET）由包括掺杂有第一导电型掺杂剂的半导体衬底内的源极区域的半导体衬底支撑。 掺杂有第一导电型掺杂剂的半导体材料的鳍具有与源极区域接触的第一端，并且还包括第二端和第二端之间的侧壁。 漏极区域由从鳍片的第二端生长并掺杂有第一导电型掺杂剂的第一外延材料形成。 栅极结构由从鳍的侧壁生长并掺杂有第二导电型掺杂剂的第二外延材料形成。