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    Semiconductor device and manufacturing method thereof
    2.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US09412819B2

    公开(公告)日：2016-08-09

    申请号：US14873185

    申请日：2015-10-01

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi Arai ,  Kenichi Hisada

    IPC: H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L21/04

    CPC classification number: H01L21/047 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

    Abstract: In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p-type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n−-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p−-type body layer, and the n−-type drift layer between the p−-type body layer and the n−-type drift layer. By those measures, it is possible to inhibit the operating characteristic from varying.

    Abstract translation: 在具有沟槽型MOS栅极结构的碳化硅半导体器件中，本发明使得可以抑制工作特性变化。 通过将p型杂质的角度离子注入到通过注入具有不同的注入能量的离子形成的p型体层而形成具有在沟槽的侧壁处的深度方向上均匀的杂质浓度分布的p型沟道层 在沟槽形成之后彼此相隔两次或更多次。 此外，虽然当通过成角度的离子注入形成p型沟道层时，p型杂质也被引入到沟槽底部的n型漂移层中，通过形成沟道长度来规定n 杂质浓度高于p型沟道层，p型体层和p型体层与n型漂移层之间的n型漂移层的杂质浓度 。 通过这些措施，可以抑制工作特性的变化。

    Semiconductor device with counter doped layer
    3.
    发明授权
    Semiconductor device with counter doped layer 有权
    具有反掺杂层的半导体器件

    公开(公告)号：US09406743B2

    公开(公告)日：2016-08-02

    申请号：US14706329

    申请日：2015-05-07

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yasuaki Kagotoshi ,  Koichi Arai ,  Natsuki Yokoyama ,  Haruka Shimizu

    IPC: H01L29/15 ,  H01L29/06 ,  H01L29/808 ,  H01L29/16 ,  H01L29/423

    CPC classification number: H01L29/0619 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/8083

    Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n−-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n−-type drift layer with a silicon oxide film formed on the n−-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n−-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n−-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

    Abstract translation: 结型场效应晶体管的制造方法包括以下步骤：（a）在n +型SiC衬底上形成的n型漂移层的表面上形成n +型源极层; （b）通过用形成在用作掩模的n型漂移层上的氧化硅膜蚀刻n型漂移层的表面，形成以预定间隔设置的多个浅沟槽; （c）通过使用垂直离子注入方法通过用氮掺杂每个浅沟槽下方的n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入法，通过用铝掺杂每个浅沟槽下的n型漂移层来形成p型栅极层。

    NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF 有权
    正常关断电源及其制造方法

    公开(公告)号：US20150060887A1

    公开(公告)日：2015-03-05

    申请号：US14536625

    申请日：2014-11-09

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi Arai ,  Yasuaki Kagotoshi ,  Nobuo Machida ,  Natsuki Yokoyama ,  Haruka Shimizu

    IPC: H01L29/808 ,  H01L29/66 ,  H01L29/16

    CPC classification number: H01L29/36 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66909 ,  H01L29/8083

    Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

    Abstract translation: 通常，在诸如基于SiC的正常关断JFET的半导体有源元件中，其中杂质扩散速度显着低于硅中的杂质扩散速度，通过离子注入形成在源区中形成的沟槽的侧壁中形成栅极区。 然而，为了确保JFET的性能，需要高精度地控制栅极区域之间的面积。 此外，存在这样的问题，由于通过在源极区域中形成栅极区域而形成重掺杂的PN结，所以不能避免结电流的增加。 本发明提供一种常闭功率JFET及其制造方法，根据多次外延法形成栅极区域，该方法重复包括外延生长，离子注入和激活退火多次的工艺。

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