公开(公告)号：US20230387011A1

公开(公告)日：2023-11-30

申请号：US17752737

申请日：2022-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Yu LU ,  Chih-Liang CHEN ,  Chia-Tien WU ,  Chih-Yu LAI ,  Shang-Hsuan CHIU

IPC: H01L23/528 ,  H01L27/085 ,  H01L21/8232 ,  H01L21/768 ,  G06F30/392

CPC classification number: H01L23/5286 ,  H01L27/085 ,  H01L21/8232 ,  H01L21/76897 ,  G06F30/392 ,  H01L23/5226

Abstract: An integrated circuit (IC) structure includes two active areas extending in a first direction, two gate structures extending in a second direction, a first metal segment extending in the second direction in a first metal layer, second and third metal segments extending in the first direction in a second metal layer, and a gate via structure extending from the third metal segment to one of the gate structures. The gate structures overlie the active areas, the first metal segment overlies each of the active areas between the gate structures, the second metal segment overlies a first active area and overlies and is electrically connected to the first metal segment, and the first and second metal segments are electrically connected to the second active area, isolated from the first active area between the gate structures, and connected to the first active area outside the gate structures.

公开(公告)号：US20230261116A1

公开(公告)日：2023-08-17

申请号：US18170034

申请日：2023-02-16

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Daping Fu ,  Yanjie Lian

IPC: H01L29/808 ,  H01L27/085 ,  H01L21/8232

CPC classification number: H01L29/808 ,  H01L27/085 ,  H01L21/8232

Abstract: A semiconductor device includes a junction field effect transistor (JFET) device. The JFET device includes a substrate, a first well region, a first source region, a first drain region, a first gate region and a second gate region. A channel region is formed between the first source region and the first drain region along a first direction. The first gate region and the second gate region are located within the channel region, the first gate region includes a first surface extending from a top surface to a bottom surface of the first gate region, and the second gate region includes a second surface extending from a top surface to a bottom surface of the second gate region. The first surface is facing a second direction perpendicular to the first direction toward the second surface. A method of manufacturing such semiconductor device is also provided.

公开(公告)号：US20180090476A1

公开(公告)日：2018-03-29

申请号：US15681721

申请日：2017-08-21

Applicant: FUJITSU LIMITED

Inventor： Youichi KAMADA

IPC: H01L27/02 ,  H01L27/095 ,  H01L29/40 ,  H01L29/778 ,  H01L21/8232 ,  H01L29/66 ,  H01L29/417 ,  H03F3/213 ,  H03F1/30 ,  H02M5/458

CPC classification number: H01L27/0211 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/0272 ,  H01L21/0274 ,  H01L21/8232 ,  H01L27/0248 ,  H01L27/095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H02M1/4225 ,  H02M3/33592 ,  H02M3/337 ,  H02M5/458 ,  H02M7/003 ,  H02M2001/007 ,  H03F1/306 ,  H03F1/3247 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F2200/451 ,  Y02B70/126 ,  Y02B70/1475

Abstract: A compound semiconductor device includes transistors each including a gate electrode, a source electrode, and a drain electrode, wherein out of the transistors, a transistor whose temperature becomes higher during operation has a higher withstand voltage prior to temperature rise due to the operation.

公开(公告)号：US20180053828A1

公开(公告)日：2018-02-22

申请号：US15794526

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mohit BAJAJ ,  Suresh GUNDAPANENI ,  Aniruddha KONAR ,  Narasimha R. Mavilla ,  Kota V.R.M. MURALI ,  Edward J. NOWAK

IPC: H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/78 ,  H01L29/772 ,  H01L29/739 ,  H01L29/66 ,  H01L29/267 ,  H01L29/24 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8232 ,  H01L21/3115

CPC classification number: H01L29/41725 ,  H01L21/02414 ,  H01L21/02483 ,  H01L21/02565 ,  H01L21/02581 ,  H01L21/3115 ,  H01L21/8232 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/205 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78693

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

公开(公告)号：US20170148783A1

公开(公告)日：2017-05-25

申请号：US14947197

申请日：2015-11-20

Applicant: Raytheon Company

Inventor： John P. Bettencourt ,  Raghuveer Mallavarpu

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/812 ,  H01L29/872 ,  H01L21/8232

CPC classification number: H01L27/0629 ,  H01L21/8232 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/8252 ,  H01L29/0696 ,  H01L29/0891 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/47 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/872 ,  H03F1/3205 ,  H03F1/3276 ,  H03F1/56 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/126 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/75

Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

公开(公告)号：US09536789B1

公开(公告)日：2017-01-03

申请号：US15007616

申请日：2016-01-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Tak H. Ning

IPC: H01L27/088 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/66 ,  H01L29/40 ,  H01L29/16

CPC classification number: H01L27/0886 ,  H01L21/3065 ,  H01L21/8232 ,  H01L27/085 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/66916 ,  H01L29/808

Abstract: A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

Abstract translation: 提供了在共同的基板上形成双门控结型场效应晶体管（JFET）和三栅极金属氧化物半导体场效应晶体管（MOSFET）的方法。 双门控JFET通过形成半导体栅极电极而形成在衬底的第一区域中，半导体栅电极接触第一半导体鳍片的第一沟道区域的侧壁表面和在第一沟道区域顶部的第一鳍片帽部分的顶表面 。 三栅极MOSFET通过形成接触第二半导体鳍片的第二沟道区域的顶表面和侧壁表面的金属栅叠层形成在衬底的第二区域中。

公开(公告)号：US20160247795A1

公开(公告)日：2016-08-25

申请号：US15144104

申请日：2016-05-02

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

公开(公告)号：US20160181237A1

公开(公告)日：2016-06-23

申请号：US15055613

申请日：2016-02-28

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Yonghai Hu ,  Meng Dai ,  Zhongyu Lin ,  Guangyang Wang

IPC: H01L27/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3205 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L27/0255 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/32055 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/8232 ,  H01L27/0248 ,  H01L29/402 ,  H01L29/66121 ,  H01L29/87

Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

Abstract translation: 静电放电保护结构包括：第一导电类型的衬底，第二导电类型的阱区，衬底中的衬底接触区域和第一类型的导电性，阱区和第二类型的阱接触区域 在衬底接触区域和阱接触区域之间的导电性，衬底反掺杂区域和第二类型的导电性，衬底接触区域和阱接触区域之间的良好的反掺杂区域以及第一类型的导电性，通信 在衬底和阱区之间的横向结合处的区域，衬底反掺杂区域和连通区域之间的第一隔离区域，阱对掺杂区域和连通区域之间的第二隔离区域， 第一隔离区和衬底上的另一端，以及氧化物层上的场板结构。

公开(公告)号：US09343589B2

公开(公告)日：2016-05-17

申请号：US14160630

申请日：2014-01-22

Applicant: GLOBALFOUNDARIES INC.

Inventor： James W. Adkisson ,  James S. Dunn ,  Blaine J. Gross ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/808 ,  H01L21/28 ,  H01L21/8232 ,  H01L29/47 ,  H01L29/66 ,  H01L29/06 ,  G06F17/50 ,  H01L21/306

CPC classification number: H01L29/808 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  H01L21/28026 ,  H01L21/306 ,  H01L21/8232 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66901 ,  H01L29/66924 ,  H01L29/7782 ,  H01L29/8124

Abstract: At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

Abstract translation: 在包括衬底，沟道和上栅极层的层堆叠中形成的至少一个隔离沟槽限定沟道层中的沟道。 来自隔离沟槽的横向蚀刻可以在衬底和上部栅极层中形成侧向空腔，以基本上同时形成自对准的下部栅极和上部栅极。 下栅极切口通道，上栅极比通道窄，并且可以在通道的相对端形成源极和漏极。 因此，可以减小源极 - 漏极电容和栅极 - 漏极电容，从而提高所产生的FET的速度。

公开(公告)号：US09293465B1

公开(公告)日：2016-03-22

申请号：US14483851

申请日：2014-09-11

Applicant: John V. Veliadis

Inventor： John V. Veliadis

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/098 ,  H01L21/8232 ,  H01L29/808 ,  H01L29/06

CPC classification number: H01L27/088 ,  G06F8/33 ,  G06F8/72 ,  G06F8/75 ,  H01L21/8232 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083

Abstract: A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.

Abstract translation: 单片双向器件提供双向功率流和双向阻断高电压。 该器件包括第一晶体管，其具有形成在覆盖衬底的第一沟道层上的第一漏极，以及第二晶体管，其包括形成在覆盖衬底的第二沟道层上的第二漏极。 衬底形成用于第一晶体管和第二晶体管的公共源极。