公开(公告)号：US20230044911A1

公开(公告)日：2023-02-09

申请号：US17436011

申请日：2021-03-03

申请人： GUANGDONG ZHINENG TECHNOLOGY CO., LTD.

发明人： Zilan LI

IPC分类号： H01L29/778 ,  H01L27/098 ,  H01L29/66 ,  H01L21/8252

摘要： The present disclosure provides an integrated circuit structure of a group III nitride semiconductor, a manufacturing method thereof, and use thereof. The integrated circuit structure is a complementary circuit of HEMT and HHMT based on the group III nitride semiconductor, and can realize the integration of HEMT and HHMT on the same substrate, and the HEMT and the HHMT respectively have a polarized junction with a vertical interface, the crystal orientations of the polarized junctions of the HEMT and the HHMT are different, the two-dimensional carrier gas forms a carrier channel in a direction parallel to the polarized junction, and corresponding channel carriers are almost depleted by burying the doped region. Compared with the conventional silicon-based CMOS, the integrated circuit structure of the present disclosure have advantages in aspects of carrier mobility, on-state current density, switching speed and so on, can realize low on-resistance, low parasitic inductance, and normally-off state of the device, and can achieve the technical effects of higher on-state current density, higher integration degree, and lower energy consumption.

公开(公告)号：US20230043191A1

公开(公告)日：2023-02-09

申请号：US17898421

申请日：2022-08-29

申请人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/098 ,  H01L23/522 ,  H01L23/367 ,  H01L27/092 ,  H01L25/00 ,  H01L23/60 ,  H01L25/065

摘要： A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming control circuitry of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth and fifth metal layers above second level; a global power distribution grid includes fifth metal, and local power distribution grid includes the second metal layer, where the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.

公开(公告)号：US20220190152A1

公开(公告)日：2022-06-16

申请号：US17688440

申请日：2022-03-07

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Hideyuki OKITA ,  Masahiro HIKITA ,  Yasuhiro UEMOTO

IPC分类号： H01L29/778 ,  H01L29/10 ,  H01L27/098 ,  H01L29/808 ,  H01L29/66

摘要： A semiconductor device includes: a substrate; a channel layer constituted of a single nitride semiconductor on the substrate; a first barrier layer which is a nitride semiconductor on a part of an upper surface of the channel layer and having a band gap larger than that of the channel layer; a gate layer which is a nitride semiconductor on and in contact with the first barrier layer; a second barrier layer which is a nitride semiconductor in contact with the first barrier layer in an area where the gate layer is not disposed above the channel layer, and having a band gap larger than that of the channel layer and having a thickness or a band gap independent from the first barrier layer; a gate electrode on the gate layer; and a source electrode and a drain electrode spaced apart from the gate layer and on the second barrier layer.

公开(公告)号：US20210118699A1

公开(公告)日：2021-04-22

申请号：US17115766

申请日：2020-12-08

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/098 ,  H01L23/522 ,  H01L23/367 ,  H01L27/092 ,  H01L25/00 ,  H01L23/60 ,  H01L25/065

摘要： A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, and where the third layer includes material other than silicon.

公开(公告)号：US10833080B2

公开(公告)日：2020-11-10

申请号：US16318001

申请日：2017-07-13

申请人： HYPERION SEMICONDUCTORS OY

发明人： Artto Aurola

IPC分类号： H01L27/092 ,  H01L27/085 ,  H01L27/098 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/12 ,  H03K19/003 ,  H03K19/0952 ,  H03K19/20 ,  H03K19/094

摘要： Disclosed is a semiconductor logic element having a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries with the described logic element.

公开(公告)号：US10777555B2

公开(公告)日：2020-09-15

申请号：US16512522

申请日：2019-07-16

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC分类号： H01L29/808 ,  H01L27/092 ,  H01L27/112 ,  H01L27/06 ,  H01L27/098 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L27/085 ,  H01L29/04

摘要： A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.

公开(公告)号：US20200185380A1

公开(公告)日：2020-06-11

申请号：US16788216

申请日：2020-02-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Takashi Ando ,  Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/098

摘要： A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

公开(公告)号：US10573648B2

公开(公告)日：2020-02-25

申请号：US15992507

申请日：2018-05-30

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC分类号： H01L29/808 ,  H01L27/092 ,  H01L27/112 ,  H01L27/06 ,  H01L27/098 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L27/085 ,  H01L29/04

摘要： A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.

公开(公告)号：US10566303B2

公开(公告)日：2020-02-18

申请号：US16209391

申请日：2018-12-04

申请人： Murata Manufacturing Co., Ltd.

发明人： Atsushi Kurokawa

IPC分类号： H01L29/80 ,  H01L23/00 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L27/082 ,  H01L29/205 ,  H01L29/45 ,  H01L27/098 ,  H01L29/423 ,  H01L29/737

摘要： A transistor includes a semiconductor region provided on a substrate and three different terminal electrodes. At least one terminal electrode has an isolated electrode structure composed of a plurality of conductor patterns. A bump, which electrically connects the plurality of conductor patterns to each other, is arranged on the terminal electrode having the isolated electrode structure. A stress-relaxing layer, which is composed of a metal material containing a high-melting-point metal, is arranged between the semiconductor region of the transistor and the bump. No current path for connecting the plurality of conductor patterns to each other is arranged between the conductor patterns and the bump.

公开(公告)号：US10553586B2

公开(公告)日：2020-02-04

申请号：US16399370

申请日：2019-04-30

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC分类号： H01L27/098 ,  H01L21/8232 ,  H01L29/66 ,  H01L29/808 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/822 ,  H01L29/06 ,  H01L27/06

摘要： A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.