公开(公告)号：US20250006798A1

公开(公告)日：2025-01-02

申请号：US18708941

申请日：2022-10-31

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki OKITA ,  Masahiro HIKITA ,  Yasuhiro UEMOTO

IPC: H01L29/20 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/207 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer provided over the substrate; a second nitride semiconductor layer that is on the first nitride semiconductor layer and includes a band gap larger than a band gap of the first nitride semiconductor layer; and a third nitride semiconductor layer that is on the second nitride semiconductor layer and includes a band gap larger than the band gap of the first nitride semiconductor layer. The second nitride semiconductor layer includes a damaged region in which an n-type impurity is selectively added by ion implantation. A diffusion region in which the n-type impurity is diffused is present in a vicinity of the damaged region. The nitride semiconductor device further includes: an ohmic electrode provided above the damaged region. The ohmic electrode is in ohmic contact with the diffusion region.

公开(公告)号：US20230386978A1

公开(公告)日：2023-11-30

申请号：US18248990

申请日：2021-08-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masayuki KURODA ,  Takahiro SATO ,  Manabu YANAGIHARA ,  Hideyuki OKITA ,  Masahiro HIKITA

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L27/02 ,  H01L23/495

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L27/0255 ,  H01L23/4952 ,  H01L23/49562

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; finger-shaped source electrodes on the second nitride semiconductor layer; finger-shaped drain electrodes disposed so as to be spaced apart from the source electrodes; and finger-shaped gate electrodes respectively disposed between the source electrodes and the drain electrodes. The gate electrodes are electrically connected, via a first gate integrated wiring, a plurality of second gate integrated wirings and a third gate integrated wiring, to gate pads located on one or both ends of the third gate integrated wiring. A plurality of source pads and the plurality of second gate integrated wirings are formed alternately in a first direction perpendicular to the longitudinal direction of the gate electrodes.

公开(公告)号：US20230361179A1

公开(公告)日：2023-11-09

申请号：US18246280

申请日：2021-08-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Masayuki KURODA ,  Hiroto YAMAGIWA ,  Hideyuki OKITA ,  Masahiro HIKITA

IPC: H01L29/20 ,  H01L29/417 ,  H01L29/866 ,  H01L23/48 ,  H01L29/861

CPC classification number: H01L29/2003 ,  H01L29/41775 ,  H01L29/866 ,  H01L23/481 ,  H01L29/8613

Abstract: A nitride semiconductor device includes: a first active area surrounded by an isolation area; and the following electrodes above the first active area: a source electrode; a first gate electrode and a second gate electrode, one on either side of and spaced from the source electrode in a first direction in plan view; and at least one drain electrode located in a direction opposite the source electrode relative to the first gate electrode or the second gate electrode. The source electrode, the first gate electrode, the second gate electrode, and the at least one drain electrode each include a finger-shaped portion extending in a second direction perpendicular to the first direction in the plan view. A first dielectric film is disposed above the source electrode. The first gate electrode and the second gate electrode are electrically connected by a gate electrode joiner disposed above the first dielectric film.

公开(公告)号：US20170117403A1

公开(公告)日：2017-04-27

申请号：US15399443

申请日：2017-01-05

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Hideyuki OKITA ,  Masahiro HIKITA ,  Hisayoshi MATSUO ,  Yasuhiro UEMOTO

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L29/0642 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/42316 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7786

Abstract: A nitride semiconductor device including a substrate, a channel layer, a carbon-poor barrier layer having a recess, a carbon-rich barrier layer disposed over the recess and the carbon-poor barrier layer, and a gate electrode above the recess, wherein the carbon-poor and carbon-rich barrier layers have bandgaps larger than that of the channel layer, the upper surface of the carbon-rich barrier layer includes a first main surface including a source electrode and a drain electrode, and a bottom surface of a depression disposed along the recess, and side surfaces of the depression connecting the first main surface to the bottom surface of the depression, and among edges of the depression of the carbon-rich barrier layer which are boundaries between the first main surface and the side surfaces of the depression, the edge of the depression of the carbon-rich barrier layer closest to the drain electrode is covered with the gate electrode.

公开(公告)号：US20220190152A1

公开(公告)日：2022-06-16

申请号：US17688440

申请日：2022-03-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki OKITA ,  Masahiro HIKITA ,  Yasuhiro UEMOTO

IPC: H01L29/778 ,  H01L29/10 ,  H01L27/098 ,  H01L29/808 ,  H01L29/66

Abstract: A semiconductor device includes: a substrate; a channel layer constituted of a single nitride semiconductor on the substrate; a first barrier layer which is a nitride semiconductor on a part of an upper surface of the channel layer and having a band gap larger than that of the channel layer; a gate layer which is a nitride semiconductor on and in contact with the first barrier layer; a second barrier layer which is a nitride semiconductor in contact with the first barrier layer in an area where the gate layer is not disposed above the channel layer, and having a band gap larger than that of the channel layer and having a thickness or a band gap independent from the first barrier layer; a gate electrode on the gate layer; and a source electrode and a drain electrode spaced apart from the gate layer and on the second barrier layer.

公开(公告)号：US20240112909A1

公开(公告)日：2024-04-04

申请号：US18264202

申请日：2022-01-04

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hisayoshi MATSUO ,  Hideyuki OKITA ,  Masahiro HIKITA ,  Yasuhiro UEMOTO ,  Manabu YANAGIHARA

IPC: H01L21/02 ,  C30B25/18 ,  C30B29/40 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L21/02505 ,  C30B25/183 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/7786

Abstract: A nitride semiconductor epitaxial substrate includes: a Si substrate; a nitride semiconductor epitaxial layer disposed above the Si substrate; and a mixed crystal layer disposed between the Si substrate and the nitride semiconductor epitaxial layer, and containing Si and a group III metal element, the mixed crystal layer containing a high concentration of C. The mixed crystal layer has a concentration of at least 1.0×10+21 cm−3, and a transition metal element concentration of at most 5.0×10+16 cm−3.

公开(公告)号：US20230411506A1

公开(公告)日：2023-12-21

申请号：US18247705

申请日：2021-10-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki OKITA ,  Manabu YANAGIHARA ,  Masahiro HIKITA

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/2003

Abstract: A nitride semiconductor device includes: a substrate; and a first nitride semiconductor layer, a second nitride semiconductor layer, and a third nitride semiconductor layer that are disposed above the substrate in the stated order. The first nitride semiconductor layer includes a recess. The second nitride semiconductor layer has a band gap larger than a band gap of the first nitride semiconductor layer and is disposed in a region other than the recess. The third nitride semiconductor layer has a band gap larger than the band gap of the first nitride semiconductor layer and covers the first nitride semiconductor layer and the second nitride semiconductor layer including an inner wall of the recess. A contact angle at which a side wall of the recess and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet ranges from 140° to less than 180°.

公开(公告)号：US20220254902A1

公开(公告)日：2022-08-11

申请号：US17626055

申请日：2020-06-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki OKITA ,  Masahiro HIKITA ,  Manabu YANAGIHARA

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A nitride semiconductor device includes a semiconductor layered structure including a substrate, a channel layer, and a barrier layer. The channel layer is formed above the substrate and made of a nitride semiconductor layer. The barrier layer is formed on the channel layer, has a wider band gap than the channel layer, and is made of a nitride semiconductor layer. The semiconductor layered structure includes an isolation region in which impurities are implanted. The position of an impurity concentration peak in the depth direction in the isolation region is deeper than the interface between the barrier layer and the channel layer. The concentration of the impurities at the interface between the barrier layer and the channel layer in the isolation region is lower than the concentration at the impurity concentration peak.