公开(公告)号：US20240048139A1

公开(公告)日：2024-02-08

申请号：US18264556

申请日：2021-10-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Koji TAKAHASHI ,  Manabu YANAGIHARA ,  Noboru NEGORO ,  Takeshi AZUMA

IPC: H03K17/30 ,  H03K17/0412 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K17/302 ,  H03K17/04123 ,  H03K19/0013 ,  H03K19/00361

Abstract: A gate drive circuit that drives a switching element including a first drain, a first source, and a first gate includes: a first terminal to which a gate control signal is input; a gate signal line connecting the first terminal and the first gate; a resistance element inserted in the gate signal line; a capacitance element connected in parallel with the resistance element; a clamp circuit that performs a clamp operation of clamping a voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and a clamp control circuit that controls whether to prohibit the clamp operation of the clamp circuit in the off period.

公开(公告)号：US20220320091A1

公开(公告)日：2022-10-06

申请号：US17630766

申请日：2020-08-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Takahiro SATO ,  Hiroto YAMAGIWA ,  Masahiro HIKITA

IPC: H01L27/095 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778

Abstract: An integrated semiconductor device includes an Si substrate, and a high-side transistor and a low-side transistor which configure a half-bridge. A source electrode of a unit transistor configuring the high-side transistor and a drain electrode of a unit transistor configuring the low-side transistor are integrated as a common electrode.

公开(公告)号：US20220302259A1

公开(公告)日：2022-09-22

申请号：US17637352

申请日：2020-08-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroto YAMAGIWA ,  Manabu YANAGIHARA ,  Takahiro SATO ,  Masahiro HIKITA ,  Hiroaki UENO ,  Yusuke KINOSHITA

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/778 ,  H01L29/10

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer above the first nitride semiconductor layer and being greater than the first nitride semiconductor layer in band gap; and a first field-effect transistor including a first source electrode, a first drain electrode, and a first gate electrode that are above the second nitride semiconductor layer, the first source electrode and the first drain electrode being separated from each other, the first gate electrode being disposed between the first source electrode and the first drain electrode. The first field-effect transistor includes a third semiconductor layer that is above the second nitride semiconductor layer in part of a region between lower part of the first source electrode and the first gate electrode, and is separated from the first gate electrode. The third semiconductor layer and the first source electrode are electrically connected.

公开(公告)号：US20180211878A1

公开(公告)日：2018-07-26

申请号：US15925050

申请日：2018-03-19

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Takahiro OHORI ,  Ayanori IKOSHI ,  Hiroto YAMAGIWA ,  Manabu YANAGIHARA

IPC: H01L21/8232 ,  H01L27/06 ,  H01L27/095 ,  H01L27/098 ,  H01L29/778 ,  H01L29/808 ,  H01L29/812 ,  H01L29/868 ,  H01L29/872

CPC classification number: H01L21/8232 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/095 ,  H01L27/098 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/747 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/808 ,  H01L29/812 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

Abstract: A semiconductor device includes: a first bidirectional switch element including a first gate electrode, a second gate electrode, a first electrode, and a second electrode; a first field-effect transistor including a third gate electrode, a third electrode, and a fourth electrode; and a second field-effect transistor including a fourth gate electrode, a fifth electrode, and a sixth electrode. The first electrode is electrically connected to the third gate electrode, the first gate electrode is electrically connected to the third electrode, the second electrode is electrically connected to the fourth gate electrode, the second gate electrode is electrically connected to the fifth electrode, and the fourth electrode is electrically connected to the sixth electrode.

公开(公告)号：US20180102426A1

公开(公告)日：2018-04-12

申请号：US15812525

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ayanori IKOSHI ,  Manabu YANAGIHARA

IPC: H01L29/778 ,  H01L29/47 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than a band gap of the first nitride semiconductor layer; a first active region which includes a source electrode, a drain electrode, and a gate electrode, and has a first carrier layer located in the first nitride semiconductor layer; and a second active region which is on an extension of a long-side direction of the drain electrode and has a second carrier layer located in the first nitride semiconductor layer via an element isolation region, and a potential of the second carrier layer is substantially same as a potential of a source extraction electrode in the second active region or is an intermediate potential between a potential of a gate extraction electrode and the potential of the source extraction electrode opposite a short side of the drain electrode.

公开(公告)号：US20220392887A1

公开(公告)日：2022-12-08

申请号：US17770010

申请日：2020-10-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Takahiro SATO ,  Hiroto YAMAGIWA ,  Masahiro HIKITA

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/872 ,  H01L29/778

Abstract: The semiconductor device includes: a semiconductor substrate; a first transistor disposed above the semiconductor substrate and including a first source electrode, a first gate region, and a first drain electrode; and a second transistor disposed above the semiconductor substrate and including a second source electrode, a second gate region, and a second drain electrode. The first source electrode, the second gate region, and the second source electrode are substantially at an identical potential. The first drain electrode and the second drain electrode are substantially at an identical potential.

公开(公告)号：US20190221503A1

公开(公告)日：2019-07-18

申请号：US16363828

申请日：2019-03-25

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Hidekazu NAKAMURA ,  Manabu YANAGIHARA ,  Tomohiko NAKAMURA ,  Yusuke KATAGIRI ,  Katsumi OTANI ,  Takeshi KAWABATA

IPC: H01L23/495 ,  H01L29/20 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/52 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/07 ,  H01L25/18 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/812 ,  H01L2224/0603 ,  H01L2224/29116 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0≤x≤1, 0≤y≤1, 0≤x+y≤1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm≥2.00×10−3×L2+0.173, tm being a thickness in mm and L being a length in mm.

公开(公告)号：US20240304630A1

公开(公告)日：2024-09-12

申请号：US18264561

申请日：2021-12-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroto YAMAGIWA ,  Manabu YANAGIHARA ,  Takahiro SATO ,  Masahiro HIKITA

IPC: H01L27/095 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L27/095 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786

Abstract: A semiconductor device includes third active regions that connect two finger-end portions of field effect transistors (FETs) spaced apart from each other, and includes, above the third active regions, portions of a third nitride semiconductor layer that includes P-type impurities.

公开(公告)号：US20240112909A1

公开(公告)日：2024-04-04

申请号：US18264202

申请日：2022-01-04

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hisayoshi MATSUO ,  Hideyuki OKITA ,  Masahiro HIKITA ,  Yasuhiro UEMOTO ,  Manabu YANAGIHARA

IPC: H01L21/02 ,  C30B25/18 ,  C30B29/40 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L21/02505 ,  C30B25/183 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/7786

Abstract: A nitride semiconductor epitaxial substrate includes: a Si substrate; a nitride semiconductor epitaxial layer disposed above the Si substrate; and a mixed crystal layer disposed between the Si substrate and the nitride semiconductor epitaxial layer, and containing Si and a group III metal element, the mixed crystal layer containing a high concentration of C. The mixed crystal layer has a concentration of at least 1.0×10+21 cm−3, and a transition metal element concentration of at most 5.0×10+16 cm−3.

公开(公告)号：US20230411506A1

公开(公告)日：2023-12-21

申请号：US18247705

申请日：2021-10-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki OKITA ,  Manabu YANAGIHARA ,  Masahiro HIKITA

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/2003

Abstract: A nitride semiconductor device includes: a substrate; and a first nitride semiconductor layer, a second nitride semiconductor layer, and a third nitride semiconductor layer that are disposed above the substrate in the stated order. The first nitride semiconductor layer includes a recess. The second nitride semiconductor layer has a band gap larger than a band gap of the first nitride semiconductor layer and is disposed in a region other than the recess. The third nitride semiconductor layer has a band gap larger than the band gap of the first nitride semiconductor layer and covers the first nitride semiconductor layer and the second nitride semiconductor layer including an inner wall of the recess. A contact angle at which a side wall of the recess and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet ranges from 140° to less than 180°.