公开(公告)号：US20220320091A1

公开(公告)日：2022-10-06

申请号：US17630766

申请日：2020-08-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Takahiro SATO ,  Hiroto YAMAGIWA ,  Masahiro HIKITA

IPC: H01L27/095 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778

Abstract: An integrated semiconductor device includes an Si substrate, and a high-side transistor and a low-side transistor which configure a half-bridge. A source electrode of a unit transistor configuring the high-side transistor and a drain electrode of a unit transistor configuring the low-side transistor are integrated as a common electrode.

公开(公告)号：US20220392887A1

公开(公告)日：2022-12-08

申请号：US17770010

申请日：2020-10-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Takahiro SATO ,  Hiroto YAMAGIWA ,  Masahiro HIKITA

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/872 ,  H01L29/778

Abstract: The semiconductor device includes: a semiconductor substrate; a first transistor disposed above the semiconductor substrate and including a first source electrode, a first gate region, and a first drain electrode; and a second transistor disposed above the semiconductor substrate and including a second source electrode, a second gate region, and a second drain electrode. The first source electrode, the second gate region, and the second source electrode are substantially at an identical potential. The first drain electrode and the second drain electrode are substantially at an identical potential.

公开(公告)号：US20240304630A1

公开(公告)日：2024-09-12

申请号：US18264561

申请日：2021-12-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroto YAMAGIWA ,  Manabu YANAGIHARA ,  Takahiro SATO ,  Masahiro HIKITA

IPC: H01L27/095 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L27/095 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786

Abstract: A semiconductor device includes third active regions that connect two finger-end portions of field effect transistors (FETs) spaced apart from each other, and includes, above the third active regions, portions of a third nitride semiconductor layer that includes P-type impurities.

公开(公告)号：US20180040706A1

公开(公告)日：2018-02-08

申请号：US15728141

申请日：2017-10-09

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Saichirou KANEKO ,  Hiroto YAMAGIWA ,  Ayanori IKOSHI ,  Masayuki KURODA ,  Manabu YANAGIHARA ,  Kenichiro TANAKA ,  Tetsuyuki FUKUSHIMA

IPC: H01L29/47 ,  H01L29/778 ,  H01L29/205 ,  H01L21/28 ,  H01L29/20 ,  H01L29/10 ,  H01L29/872 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/475 ,  H01L21/28 ,  H01L29/0619 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

公开(公告)号：US20160351676A1

公开(公告)日：2016-12-01

申请号：US15234775

申请日：2016-08-11

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Saichirou KANEKO ,  Hiroto YAMAGIWA ,  Ayanori IKOSHI ,  Masayuki KURODA ,  Manabu YANAGIHARA ,  Kenichiro TANAKA ,  Tetsuyuki FUKUSHIMA

IPC: H01L29/47 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778 ,  H01L29/872

CPC classification number: H01L29/475 ,  H01L21/28 ,  H01L29/0619 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

公开(公告)号：US20230361179A1

公开(公告)日：2023-11-09

申请号：US18246280

申请日：2021-08-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Masayuki KURODA ,  Hiroto YAMAGIWA ,  Hideyuki OKITA ,  Masahiro HIKITA

IPC: H01L29/20 ,  H01L29/417 ,  H01L29/866 ,  H01L23/48 ,  H01L29/861

CPC classification number: H01L29/2003 ,  H01L29/41775 ,  H01L29/866 ,  H01L23/481 ,  H01L29/8613

Abstract: A nitride semiconductor device includes: a first active area surrounded by an isolation area; and the following electrodes above the first active area: a source electrode; a first gate electrode and a second gate electrode, one on either side of and spaced from the source electrode in a first direction in plan view; and at least one drain electrode located in a direction opposite the source electrode relative to the first gate electrode or the second gate electrode. The source electrode, the first gate electrode, the second gate electrode, and the at least one drain electrode each include a finger-shaped portion extending in a second direction perpendicular to the first direction in the plan view. A first dielectric film is disposed above the source electrode. The first gate electrode and the second gate electrode are electrically connected by a gate electrode joiner disposed above the first dielectric film.

公开(公告)号：US20160043208A1

公开(公告)日：2016-02-11

申请号：US14887249

申请日：2015-10-19

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Ayanori IKOSHI ,  Hiroto YAMAGIWA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40

CPC classification number: H01L29/778 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/7786

Abstract: A nitride semiconductor device includes the followings. A semiconductor multilayer structure is above a substrate and includes a first nitride semiconductor layer and a second nitride semiconductor layer. A source electrode, a drain electrode, and a gate electrode are on the semiconductor multilayer structure. A gate wiring line transmits a gate driving signal to gate electrodes. A first shield structure is on the semiconductor multilayer structure between the drain electrode and the gate electrode or between the drain electrode and the gate wiring line in a non-channel region where an actual current path from the drain electrode to the source electrode is not formed in the semiconductor multilayer structure. The first shield structure is a normally-off structure, suppresses a current flowing from the semiconductor multilayer structure, and is set to have a substantially same potential as a potential of the source electrode.

Abstract translation: 氮化物半导体器件包括以下。 半导体多层结构在衬底之上，并且包括第一氮化物半导体层和第二氮化物半导体层。 源电极，漏电极和栅电极在半导体多层结构上。 栅极布线将栅极驱动信号传输到栅电极。 第一屏蔽结构在漏极电极和栅电极之间的半导体层叠结构上，或者在不形成从漏电极到源电极的实际电流路径的非沟道区域中的漏电极和栅极布线之间 在半导体多层结构中。 第一屏蔽结构是常关结构，抑制从半导体多层结构流过的电流，并且被设定为具有与源电极的电位大致相同的电位。

公开(公告)号：US20220302259A1

公开(公告)日：2022-09-22

申请号：US17637352

申请日：2020-08-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroto YAMAGIWA ,  Manabu YANAGIHARA ,  Takahiro SATO ,  Masahiro HIKITA ,  Hiroaki UENO ,  Yusuke KINOSHITA

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/778 ,  H01L29/10

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer above the first nitride semiconductor layer and being greater than the first nitride semiconductor layer in band gap; and a first field-effect transistor including a first source electrode, a first drain electrode, and a first gate electrode that are above the second nitride semiconductor layer, the first source electrode and the first drain electrode being separated from each other, the first gate electrode being disposed between the first source electrode and the first drain electrode. The first field-effect transistor includes a third semiconductor layer that is above the second nitride semiconductor layer in part of a region between lower part of the first source electrode and the first gate electrode, and is separated from the first gate electrode. The third semiconductor layer and the first source electrode are electrically connected.

公开(公告)号：US20180211878A1

公开(公告)日：2018-07-26

申请号：US15925050

申请日：2018-03-19

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Takahiro OHORI ,  Ayanori IKOSHI ,  Hiroto YAMAGIWA ,  Manabu YANAGIHARA

IPC: H01L21/8232 ,  H01L27/06 ,  H01L27/095 ,  H01L27/098 ,  H01L29/778 ,  H01L29/808 ,  H01L29/812 ,  H01L29/868 ,  H01L29/872

CPC classification number: H01L21/8232 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/095 ,  H01L27/098 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/747 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/808 ,  H01L29/812 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

Abstract: A semiconductor device includes: a first bidirectional switch element including a first gate electrode, a second gate electrode, a first electrode, and a second electrode; a first field-effect transistor including a third gate electrode, a third electrode, and a fourth electrode; and a second field-effect transistor including a fourth gate electrode, a fifth electrode, and a sixth electrode. The first electrode is electrically connected to the third gate electrode, the first gate electrode is electrically connected to the third electrode, the second electrode is electrically connected to the fourth gate electrode, the second gate electrode is electrically connected to the fifth electrode, and the fourth electrode is electrically connected to the sixth electrode.