公开(公告)号：US20230154986A1

公开(公告)日：2023-05-18

申请号：US18097586

申请日：2023-01-17

申请人： FUJI ELECTRIC CO., LTD.

发明人： Keiji OKUMURA

IPC分类号： H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/16 ,  H01L29/745

CPC分类号： H01L29/1095 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7806 ,  H01L29/0865 ,  H01L29/7811 ,  H01L29/4236 ,  H01L29/417 ,  H01L29/66068 ,  H01L29/1608 ,  H01L29/745 ,  H01L29/083 ,  H01L29/66348 ,  H01L21/049

摘要： An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

公开(公告)号：US20180158935A1

公开(公告)日：2018-06-07

申请号：US15371512

申请日：2016-12-07

申请人： QUALCOMM Incorporated

发明人： Hao Wang ,  Haining Yang ,  Xiaonan Chen

IPC分类号： H01L29/739 ,  H01L27/02 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7391 ,  H01L27/0255 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/495 ,  H01L29/66356 ,  H01L29/7851

摘要： Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.

公开(公告)号：US20180145134A1

公开(公告)日：2018-05-24

申请号：US15706554

申请日：2017-09-15

申请人： Renesas Electronics Corporation

发明人： Nao NAGATA

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/0696 ,  H01L29/0619 ,  H01L29/083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397

摘要： An improvement is achieved in the IE effect of a semiconductor device including an IGBT having an active cell region with an EGE structure. Each of a plurality of hybrid cell regions extending in a Y-axis direction has first, second, and third trench electrodes extending in the Y-axis direction, a p-type body region, and contact trenches provided between the first and second trench electrodes and between the first and third trench electrodes to extend in the Y-axis direction and reach middle points in the p-type body region. Each of the hybrid cell regions further has a plurality of n+-type emitter regions formed in an upper surface of a semiconductor substrate located between the contact trenches and the first trench electrode to be shallower than the contact trenches and spaced apart at regular intervals in the Y-direction in plan view. The n+-type emitter regions are arranged in a staggered configuration in plan view.

公开(公告)号：US09947586B2

公开(公告)日：2018-04-17

申请号：US15042908

申请日：2016-02-12

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L29/165 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785

摘要： A method of forming semiconductor devices may begin with forming gate structures over fin structures on sidewalls of at least two mandrels. The mandrels are removed to provide gate structures having a first pitch and gate structure spacers having a second pitch. A first conductivity type epitaxial semiconductor material is formed on the exposed portions of the fin structures. Masking is formed in the first pitch space. The first conductivity type epitaxial semiconductor material is removed from a second space pitch. A second conductivity type epitaxial semiconductor material is formed in the second space pitch.

公开(公告)号：US20180083129A1

公开(公告)日：2018-03-22

申请号：US15446642

申请日：2017-03-01

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Mitsuhiko KITAGAWA

IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36

CPC分类号： H01L29/7395 ,  H01L21/743 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/083 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66181 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/945

摘要： A semiconductor device includes a first electrode, a first semiconductor region disposed on and electrically connected to the first electrode, a second semiconductor region disposed on the first semiconductor region and having a carrier concentration lower than that of the first semiconductor region, a third semiconductor region disposed on the second semiconductor region, a fourth semiconductor region disposed on the third semiconductor region, a fifth semiconductor region disposed on the second semiconductor region and separated from the third semiconductor region in a direction, a gate electrode disposed on the second semiconductor region, facing the third semiconductor region via an insulating layer in the direction and positioned between the third and fourth semiconductor regions, a second electrode disposed on and electrically connected to the fourth semiconductor region, and a third electrode disposed on the fifth semiconductor region, separated from the second electrode, and electrically connected to the fifth semiconductor region.

公开(公告)号：US20180026121A1

公开(公告)日：2018-01-25

申请号：US15655715

申请日：2017-07-20

申请人： Pakal Technologies, LLC

发明人： Richard A. Blanchard ,  Vladimir Rodov ,  Hidenori Akiyama ,  Woytek Tworzydlo

IPC分类号： H01L29/739 ,  H01L27/07 ,  H01L29/08 ,  H01L29/47 ,  H01L29/10

CPC分类号： H01L29/7396 ,  H01L27/0716 ,  H01L29/083 ,  H01L29/0839 ,  H01L29/105 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7455 ,  H01L29/7813 ,  H01L29/7839

摘要： An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the npn transistor to its emitter, to turn the npn transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. The p-channel MOSFET includes a Schottky source formed in the top surface of the npn transistor emitter.

公开(公告)号：US09876084B2

公开(公告)日：2018-01-23

申请号：US15084144

申请日：2016-03-29

申请人： International Business Machines Corporation

发明人： Mohit Bajaj ,  Suresh Gundapaneni ,  Aniruddha Konar ,  Narasimha R. Mavilla ,  Kota V. R. M. Murali ,  Edward J. Nowak

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L21/02 ,  H01L29/786 ,  H01L29/772 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/24 ,  H01L21/3115 ,  H01L21/8232 ,  H01L21/8234

CPC分类号： H01L29/41725 ,  H01L21/02414 ,  H01L21/02483 ,  H01L21/02565 ,  H01L21/02581 ,  H01L21/3115 ,  H01L21/8232 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/205 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78693

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

公开(公告)号：US20170222400A1

公开(公告)日：2017-08-03

申请号：US15450400

申请日：2017-03-06

申请人： THE UNIVERSITY OF CONNECTICUT ,  Opel Solar, Inc.

发明人： Geoff W. TAYLOR

IPC分类号： H01S5/10 ,  G02B6/134 ,  G02B6/13 ,  H01S5/042 ,  H01S5/062 ,  H01L31/18 ,  H01S5/30 ,  H01L31/0352 ,  H01L31/0304 ,  H01L31/112 ,  H01L31/11 ,  H01L31/0232 ,  G02B6/293 ,  H01S5/20

CPC分类号： H01S5/1071 ,  G02B6/131 ,  G02B6/1347 ,  G02B6/29338 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L27/1443 ,  H01L29/083 ,  H01L29/1066 ,  H01L29/15 ,  H01L29/36 ,  H01L29/66401 ,  H01L29/74 ,  H01L29/7783 ,  H01L31/02327 ,  H01L31/03046 ,  H01L31/035209 ,  H01L31/035236 ,  H01L31/1105 ,  H01L31/1113 ,  H01L31/1129 ,  H01L31/1844 ,  H01L33/06 ,  H01L33/105 ,  H01S5/0228 ,  H01S5/0421 ,  H01S5/0424 ,  H01S5/0425 ,  H01S5/06203 ,  H01S5/06226 ,  H01S5/0625 ,  H01S5/1028 ,  H01S5/1032 ,  H01S5/1042 ,  H01S5/1075 ,  H01S5/125 ,  H01S5/183 ,  H01S5/187 ,  H01S5/2027 ,  H01S5/2063 ,  H01S5/2086 ,  H01S5/222 ,  H01S5/3054 ,  H01S5/309 ,  H01S5/34313

摘要： A semiconductor device includes an n-type ohmic contact layer, cathode and anode electrodes, p-type and n-type modulation doped quantum well (QW) structures, and first and second ion implant regions. The anode electrode is formed on the first ion implant region that contacts the p-type modulation doped QW structure and the cathode electrode is formed by patterning the first and second ion implant regions and the n-type ohmic contact layer. The semiconductor device is configured to operate as at least one of a diode laser and a diode detector. As the diode laser, the semiconductor device emits photons. As the diode detector, the semiconductor device receives an input optical light and generates a photocurrent.

公开(公告)号：US20170148904A1

公开(公告)日：2017-05-25

申请号：US15359259

申请日：2016-11-22

申请人： Infineon Technologies AG

发明人： Roman Baburske ,  Johannes Georg Laven ,  Hans-Joachim Schulze ,  Antonio Vellei

IPC分类号： H01L29/739 ,  H01L29/08 ,  H01L29/866 ,  H01L27/06 ,  H01L29/10

CPC分类号： H01L29/7397 ,  H01L27/0664 ,  H01L27/0727 ,  H01L29/0804 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/866

摘要： A transistor includes first and second load terminals and a semiconductor body coupled to both terminals. The semiconductor body includes: a drift region having dopants of a first conductivity type; a transistor section for conducting a forward load current and having a control head coupling the first load terminal to a first side of the drift region; and a diode section for conducting a reverse load current. A diode port couples the second load terminal to a second side of the drift region and includes: a first emitter electrically connected to the second load terminal and having dopants of the first conductivity type for injecting majority charge carriers into the drift region; and a second emitter having dopants of a second conductivity type for injecting minority charge carriers into the drift region. A pn-junction transition between the first and second emitters has a breakdown voltage of less than 10 V.

公开(公告)号：US20170148795A1

公开(公告)日：2017-05-25

申请号：US15426588

申请日：2017-02-07

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： H01L27/102 ,  H01L21/8249

CPC分类号： H01L27/1025 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76229 ,  H01L21/768 ,  H01L21/8229 ,  H01L21/8249 ,  H01L23/528 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/083 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7436 ,  H01L2924/0002 ,  H01L2924/00

摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.