公开(公告)号：US10340370B2

公开(公告)日：2019-07-02

申请号：US15371512

申请日：2016-12-07

Applicant: QUALCOMM Incorporated

Inventor： Hao Wang ,  Haining Yang ,  Xiaonan Chen

IPC: H01L29/739 ,  H01L27/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.

公开(公告)号：US20180158935A1

公开(公告)日：2018-06-07

申请号：US15371512

申请日：2016-12-07

Applicant: QUALCOMM Incorporated

Inventor： Hao Wang ,  Haining Yang ,  Xiaonan Chen

IPC: H01L29/739 ,  H01L27/02 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7391 ,  H01L27/0255 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/495 ,  H01L29/66356 ,  H01L29/7851

Abstract: Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.