公开(公告)号：US09691908B2

公开(公告)日：2017-06-27

申请号：US14870922

申请日：2015-09-30

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Kenichi Hisada ,  Koichi Arai

IPC分类号： H01L29/808 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L27/098

CPC分类号： H01L29/8083 ,  H01L27/098 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66037

摘要： In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.

公开(公告)号：US09337327B2

公开(公告)日：2016-05-10

申请号：US14750196

申请日：2015-06-25

申请人： Renesas Electronics Corporation

发明人： Koichi Arai ,  Masaki Hama ,  Yasuaki Kagotoshi ,  Kenichi Hisada

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L21/04

CPC分类号： H01L29/7811 ,  H01L21/02236 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/049 ,  H01L21/31111 ,  H01L21/32105 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816

摘要： The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

摘要翻译： 本发明可以通过在湿蚀刻上在衬底上打开绝缘膜来指定在SiC衬底上形成的垂直型功率MOSFET的有源区，提高湿式蚀刻的精度​​和使半导体器件的小型化。 在外延层上依次形成膜厚小的氧化硅膜和膜厚度大于氧化硅膜的多晶硅膜，通过干式蚀刻方法打开多晶硅膜，依次将氧化硅膜为 通过湿蚀刻方法打开，从而暴露有源区中的外延层的上表面。

公开(公告)号：US10896980B2

公开(公告)日：2021-01-19

申请号：US16598832

申请日：2019-10-10

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yasuhiro Okamoto ,  Nobuo Machida ,  Kenichi Hisada

IPC分类号： H01L29/872 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/16 ,  H01L29/47

摘要： In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

公开(公告)号：US09412819B2

公开(公告)日：2016-08-09

申请号：US14873185

申请日：2015-10-01

申请人： Renesas Electronics Corporation

发明人： Koichi Arai ,  Kenichi Hisada

IPC分类号： H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L21/04

CPC分类号： H01L21/047 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

摘要： In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p-type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n−-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p−-type body layer, and the n−-type drift layer between the p−-type body layer and the n−-type drift layer. By those measures, it is possible to inhibit the operating characteristic from varying.

摘要翻译： 在具有沟槽型MOS栅极结构的碳化硅半导体器件中，本发明使得可以抑制工作特性变化。 通过将p型杂质的角度离子注入到通过注入具有不同的注入能量的离子形成的p型体层而形成具有在沟槽的侧壁处的深度方向上均匀的杂质浓度分布的p型沟道层 在沟槽形成之后彼此相隔两次或更多次。 此外，虽然当通过成角度的离子注入形成p型沟道层时，p型杂质也被引入到沟槽底部的n型漂移层中，通过形成沟道长度来规定n 杂质浓度高于p型沟道层，p型体层和p型体层与n型漂移层之间的n型漂移层的杂质浓度 。 通过这些措施，可以抑制工作特性的变化。

公开(公告)号：US10109733B2

公开(公告)日：2018-10-23

申请号：US15627333

申请日：2017-06-19

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yasunori Yamashita ,  Koichi Arai ,  Kenichi Hisada

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66

摘要： In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of a part of the gate insulating film part formed on/over a side face of the trench.

公开(公告)号：US09184238B2

公开(公告)日：2015-11-10

申请号：US14270469

申请日：2014-05-06

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Kenichi Hisada ,  Koichi Arai

IPC分类号： H01L29/16 ,  H01L29/808 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/8083 ,  H01L27/098 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66037

摘要： In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.

摘要翻译： 为了确保杂质扩散率低于硅基的SiC基JFET的性能，确保栅极深度，同时精确地控制栅极区域之间的距离，而不是通过离子注入形成栅极区域到侧壁 的沟渠 这意味着由栅极距离和栅极深度限定的沟道区域应具有高的纵横比。 此外，由于处理的限制，在源极区域内形成栅极区域。 在源极和栅极区域之间形成高度掺杂的PN结导致各种问题，例如结电流的不可避免的增加。 此外，为了形成端接结构，需要显着高能量的离子注入。 在本发明中，提供了一种垂直沟道型SiC功率JFET，其具有位于源极区域之下和栅极区域之下并与源极区分离的浮动栅极区域。

公开(公告)号：US10833188B2

公开(公告)日：2020-11-10

申请号：US16282981

申请日：2019-02-22

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Kenichi Hisada ,  Koichi Arai ,  Hironobu Miyamoto

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266

摘要： First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

公开(公告)号：US10468496B2

公开(公告)日：2019-11-05

申请号：US15790195

申请日：2017-10-23

申请人： Renesas Electronics Corporation

发明人： Kenichi Hisada ,  Koichi Arai

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L23/31 ,  H01L29/78 ,  H01L21/04 ,  H01L21/02 ,  H01L23/29 ,  H01L29/739 ,  H01L29/51

摘要： A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.

公开(公告)号：US09570602B2

公开(公告)日：2017-02-14

申请号：US15095469

申请日：2016-04-11

申请人： Renesas Electronics Corporation

发明人： Koichi Arai ,  Masaki Hama ,  Yasuaki Kagotoshi ,  Kenichi Hisada

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L21/04 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7811 ,  H01L21/02236 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/049 ,  H01L21/31111 ,  H01L21/32105 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816

摘要： The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

摘要翻译： 本发明可以通过在湿蚀刻上在衬底上打开绝缘膜来指定在SiC衬底上形成的垂直型功率MOSFET的有源区，提高湿式蚀刻的精度​​和使半导体器件的小型化。 在外延层上依次形成膜厚小的氧化硅膜和膜厚度大于氧化硅膜的多晶硅膜，通过干式蚀刻方法打开多晶硅膜，依次将氧化硅膜为 通过湿蚀刻方法打开，从而暴露有源区中的外延层的上表面。

公开(公告)号：US11631764B2

公开(公告)日：2023-04-18

申请号：US17060486

申请日：2020-10-01

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Kenichi Hisada ,  Koichi Arai ,  Hironobu Miyamoto

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266

摘要： First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.