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    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150221757A1

    公开(公告)日：2015-08-06

    申请号：US14604796

    申请日：2015-01-26

    申请人： Renesas Electronics Corporation

    发明人： Tatsuo NAKAYAMA ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

    IPC分类号： H01L29/778 ,  H01L23/522 ,  H01L29/15

    CPC分类号： H01L29/7783 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

    摘要翻译： 提高了半导体器件的特性。 半导体器件被配置为提供穿透阻挡层的沟槽，并且到达n +层，n型层，p型层，沟道层和势垒层中的沟道层的中间部分，其中 形成在基板上方，通过栅极绝缘膜布置在沟槽内的栅电极，以及形成在栅电极两侧的势垒层上方的源电极和漏电极。 n型层和漏电极通过到达n +层的连接部分彼此电耦合。 p型层和源电极通过到达p型层的连接部分彼此电耦合。 在源电极和漏电极之间设置包括p型层和n型层的二极管，从而防止由雪崩击穿引起的元件断裂。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140239311A1

    公开(公告)日：2014-08-28

    申请号：US14188462

    申请日：2014-02-24

    申请人： Renesas Electronics Corporation

    发明人： Tohru Kawai ,  Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

    IPC分类号： H01L29/778 ,  H01L29/20

    CPC分类号： H01L29/778 ,  H01L21/76895 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789

    摘要： A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-type impurity concentration larger than a region of the channel layer positioned on a barrier layer side, and the buffer layer is made of nitride semiconductor having a band gap wider than that of the channel layer. The channel layer is made of GaN and the buffer layer is made of AlGaN. The channel layer has a channel lower layer containing n-type impurities at an intermediate concentration and a main channel layer formed thereon and containing n-type impurities at a low concentration.

    摘要翻译： 半导体器件包括缓冲层，沟道层和在衬底上形成的势垒层，穿过势垒层的沟槽到达沟道层的中间，以及通过栅极绝缘膜设置在沟槽内的栅电极。 沟道层含有n型杂质，位于缓冲层侧的沟道层的区域的n型杂质浓度大于位于势垒层侧的沟道层的区域，并且形成缓冲层 的氮化物半导体具有比沟道层宽的带隙。 沟道层由GaN制成，缓冲层由AlGaN制成。 沟道层具有含有中等浓度的n型杂质的沟道下层和形成在其上的主沟道层并且含有低浓度的n型杂质。

    Manufacturing method of semiconductor device
    6.
    发明授权
    Manufacturing method of semiconductor device 有权

    公开(公告)号：US10541321B2

    公开(公告)日：2020-01-21

    申请号：US16028128

    申请日：2018-07-05

    申请人： Renesas Electronics Corporation

    发明人： Yasuhiro Okamoto

    IPC分类号： H01L21/00 ,  H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L23/532 ,  H01L29/417 ,  H01L29/00 ,  H01L29/20

    摘要： In a manufacturing method of a semiconductor device according to the present invention, a buffer layer including a first nitride semiconductor layer, a channel layer including a second nitride semiconductor layer, and a barrier layer including a third nitride semiconductor layer are sequentially laminated, and a fourth nitride semiconductor layer is further laminated thereover. Then, a laminate of a gate insulating film and a gate electrode is formed over a first region of the fourth nitride semiconductor layer, and a silicon nitride film is formed over the fourth nitride semiconductor layer and the laminate. By bringing the fourth nitride semiconductor layers on both sides of the gate electrode into contact with the silicon nitride film in this way, the function of suppressing 2DEG can be lowered, and the 2DEG that has been eliminated after the formation of the fourth nitride semiconductor layer can be restored. The lowering in the function of suppressing 2DEG is maintained even after the silicon nitride film is removed.

    Semiconductor device and method of manufacturing semiconductor device
    8.
    发明授权
    Semiconductor device and method of manufacturing semiconductor device 有权

    公开(公告)号：US10396190B2

    公开(公告)日：2019-08-27

    申请号：US15985987

    申请日：2018-05-22

    申请人： RENESAS ELECTRONICS CORPORATION

    发明人： Takehiro Ueda ,  Yasuhiro Okamoto

    IPC分类号： H01L29/778 ,  H01L21/265 ,  H01L21/308 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

    摘要： Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part.

    Semiconductor device and manufacturing method of semiconductor device
    9.
    发明授权
    Semiconductor device and manufacturing method of semiconductor device 有权

    公开(公告)号：US10199476B2

    公开(公告)日：2019-02-05

    申请号：US15841676

    申请日：2017-12-14

    申请人： Renesas Electronics Corporation

    发明人： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto

    IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L29/10 ,  H01L29/20 ,  H01L29/40 ,  H01L29/207

    摘要： A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.