公开(公告)号：US11387334B2

公开(公告)日：2022-07-12

申请号：US16858276

申请日：2020-04-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro Ueda

IPC: H01L29/417 ,  C23C18/16 ,  H01L21/288

Abstract: The semiconductor device includes a first electrode, a second electrode electrically coupled to the first electrode, and a third electrodes electrically coupled to at least one of the first and the second electrode, a first plating deposition portion on the first electrode, a second and a third plating deposition portions formed on the second and the third electrode, respectively. The areas of the second and the third plating deposition portion are smaller than the area of the first plating deposition portion. The periphery length of the third plating deposition portion is longer than the periphery length of the second plating deposition portion.

公开(公告)号：US10135435B2

公开(公告)日：2018-11-20

申请号：US15797062

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Takehiro Ueda

IPC: H03K17/16 ,  H02M1/34 ,  H02M7/5387

Abstract: A high side transistor is coupled between a high potential side power source node and an intermediate node, and a recirculation diode is coupled between a low potential side power source node and the intermediate node, thereby forming a recirculation path when the high side transistor is OFF. A power source supply line couples the high potential side power source node with one end of the high side transistor. A surge recirculation device causes a current to flow in one direction, and a surge recirculation line couples the one end of the high side transistor to the high potential side power source node through the surge recirculation device, and causes a surge generated at the one end of the high side transistor to recirculate toward the high potential side power source node.

公开(公告)号：US08742465B2

公开(公告)日：2014-06-03

申请号：US13630467

申请日：2012-09-28

Applicant: Renesas Electronics Corporation

Inventor： Takehiro Ueda

IPC: H01L23/52

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract translation: 一种切割包括第一导体和第二导体的电熔丝的方法，所述第一导体包括第一切割目标区域，所述第二导体从所述第一导体分支并连接到所述第一导体并且包括第二切割目标区域，所述第二切割目标区域是 形成在半导体衬底上，该方法包括使第一导体中的电流流动，使得第一导体的材料在连接第一导体与第二导体的耦合部分附近向外流动，以及切割第一切割目标区域和第二切割 目标区域。

公开(公告)号：US20130288445A1

公开(公告)日：2013-10-31

申请号：US13926109

申请日：2013-06-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro Ueda ,  Hiroshi Kawaguchi

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region.

Abstract translation: 一种制造包括晶体管的半导体器件的方法。 该方法包括通过将第二导电类型的杂质离子注入到形成在衬底的一侧上的元件形成区域并由元件隔离绝缘膜分隔而形成沟道区域，在所述沟道区域中形成沟槽， 通过在所述衬底的所述一侧上形成所述栅极绝缘膜，形成栅电极以掩埋所述沟槽的内部，形成图案化的所述衬底的一侧，覆盖所述沟槽的侧面和所述沟槽的底面，并具有栅极绝缘膜 所述栅电极为预定形状; 以及通过在所述沟道区的两侧注入第一导电类型的杂质离子而形成源区和漏区。

公开(公告)号：US09620449B2

公开(公告)日：2017-04-11

申请号：US14878216

申请日：2015-10-08

Applicant: Renesas Electronics Corporation

Inventor： Takehiro Ueda

IPC: H01L27/10 ,  H01L23/525 ,  H01L23/34 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L23/345 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

公开(公告)号：US09177912B2

公开(公告)日：2015-11-03

申请号：US14086268

申请日：2013-11-21

Applicant: Renesas Electronics Corporation

Inventor： Takehiro Ueda

IPC: H01L27/10 ,  H01L23/525 ,  H01L23/34

CPC classification number: H01L23/5256 ,  H01L23/345 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Abstract translation: 保险丝的熔融部分被板包围，使得在电流供应下在熔断器的熔化部分产生的热可以被限制或积聚在熔断器的熔化部分附近。 这使得可以促进保险丝熔断。 熔断器的熔化部分是折叠形式，而不是在这里单个由直线形式组成的保险丝，更容易将电流供应中产生的保险丝中的热量集中到熔化部分中，而且在另外 有助于保险丝熔断。

公开(公告)号：US08871592B2

公开(公告)日：2014-10-28

申请号：US13926109

申请日：2013-06-25

Applicant: Renesas Electronics Corporation

Inventor： Takehiro Ueda ,  Hiroshi Kawaguchi

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/78 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region.

Abstract translation: 一种制造包括晶体管的半导体器件的方法。 该方法包括通过将第二导电类型的杂质离子注入到形成在衬底的一侧上的元件形成区域并由元件隔离绝缘膜分隔而形成沟道区域，在所述沟道区域中形成沟槽， 通过在所述衬底的所述一侧上形成所述栅极绝缘膜，形成栅电极以埋设所述沟槽的内部，形成图案化的所述衬底的一侧，覆盖具有栅极绝缘膜的所述沟槽的侧面和底面 所述栅电极为预定形状; 以及通过在所述沟道区的两侧注入第一导电类型的杂质离子而形成源区和漏区。

公开(公告)号：US10396190B2

公开(公告)日：2019-08-27

申请号：US15985987

申请日：2018-05-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro Ueda ,  Yasuhiro Okamoto

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/308 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part.

公开(公告)号：US10396153B2

公开(公告)日：2019-08-27

申请号：US15889244

申请日：2018-02-06

Applicant: Renesas Electronics Corporation

Inventor： Takehiro Ueda

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/205 ,  H01L21/265 ,  H01L29/778 ,  H01L29/66 ,  H01L21/761 ,  H01L29/40 ,  H01L29/423 ,  H01L29/20

Abstract: A high-electron-mobility transistor has a buffer layer, a channel layer, a barrier layer, a mesa-shaped cap layer, a source electrode formed on one side of the cap layer, a drain electrode formed on the other side, and a gate electrode formed over the cap layer via a gate insulating film. The semiconductor device has an element isolation region defining an active region in which the semiconductor device is provided. The gate electrode extends from over the active region to the over the element isolation region. In plan view, the active region has a projection part projected to the direction of the element isolation region in a region overlapped with the gate electrode. By providing the active region with a projection part, the channel length of a parasitic transistor can be increased, and turn-on of the parasitic transistor can be suppressed.

公开(公告)号：US12289918B2

公开(公告)日：2025-04-29

申请号：US17463150

申请日：2021-08-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro Ueda

IPC: H10D84/00 ,  H01L23/522 ,  H10D89/10 ,  H10D30/01 ,  H10D64/01

Abstract: The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.