公开(公告)号：US08871592B2

公开(公告)日：2014-10-28

申请号：US13926109

申请日：2013-06-25

Applicant: Renesas Electronics Corporation

Inventor： Takehiro Ueda ,  Hiroshi Kawaguchi

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/78 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region.

Abstract translation: 一种制造包括晶体管的半导体器件的方法。 该方法包括通过将第二导电类型的杂质离子注入到形成在衬底的一侧上的元件形成区域并由元件隔离绝缘膜分隔而形成沟道区域，在所述沟道区域中形成沟槽， 通过在所述衬底的所述一侧上形成所述栅极绝缘膜，形成栅电极以埋设所述沟槽的内部，形成图案化的所述衬底的一侧，覆盖具有栅极绝缘膜的所述沟槽的侧面和底面 所述栅电极为预定形状; 以及通过在所述沟道区的两侧注入第一导电类型的杂质离子而形成源区和漏区。

公开(公告)号：US09984884B2

公开(公告)日：2018-05-29

申请号：US15385507

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/04 ,  H01L29/778 ,  H01L21/28 ,  H01L21/02 ,  H01L21/308 ,  H01L29/423 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.

公开(公告)号：US09853108B2

公开(公告)日：2017-12-26

申请号：US15394882

申请日：2016-12-30

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Kawaguchi

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/408 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/423 ,  H01L29/4234 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/66833 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/792

Abstract: The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased.

公开(公告)号：US09559173B2

公开(公告)日：2017-01-31

申请号：US14827880

申请日：2015-08-17

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Kawaguchi

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/792

CPC classification number: H01L29/408 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/423 ,  H01L29/4234 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/66833 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/792

Abstract: The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased.

Abstract translation: 半导体器件包括：沟道层，阻挡层，第一绝缘膜和第二绝缘膜，其各自形成在衬底上; 穿过第二绝缘膜，第一绝缘膜和阻挡层的沟槽，以到达沟道层的中间; 以及栅电极，其经由栅极绝缘膜布置在所述沟槽中并且在所述第二绝缘膜上方。 第二绝缘膜的带隙小于第一绝缘膜的带隙，第二绝缘膜的带隙小于栅极绝缘膜GI的带隙。 因此，可以在第二（上）绝缘膜中积累电荷（电子），从而提高沟槽角部的电场强度。 结果，甚至在沟槽的拐角处完全形成沟道，从而允许导通电阻降低并且导通电流增加。

公开(公告)号：US20180151377A1

公开(公告)日：2018-05-31

申请号：US15882687

申请日：2018-01-29

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/28 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308 ,  H01L29/20

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.

公开(公告)号：US09831339B2

公开(公告)日：2017-11-28

申请号：US15632663

申请日：2017-06-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Ichiro Masumoto ,  Yasuhiro Okamoto ,  Shinichi Miyake ,  Hiroshi Kawaguchi

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US09722062B2

公开(公告)日：2017-08-01

申请号：US14837053

申请日：2015-08-27

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Ichiro Masumoto ,  Yasuhiro Okamoto ,  Shinichi Miyake ,  Hiroshi Kawaguchi

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/207 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170103898A1

公开(公告)日：2017-04-13

申请号：US15385507

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi INOUE ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/28 ,  H01L29/778 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.

公开(公告)号：US09559183B2

公开(公告)日：2017-01-31

申请号：US14271277

申请日：2014-05-06

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/201 ,  H01L29/205 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/336 ,  H01L29/45 ,  H01L29/20

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.

Abstract translation: 提供具有改进特性的半导体器件。 半导体器件具有衬底，其上具有缓冲层，沟道层，阻挡层，穿透其中并到达沟道层内部的沟槽，通过栅极绝缘膜放置在沟槽中的栅电极，以及漏极和源极 位于栅电极两侧的阻挡层上的电极。 栅极绝缘膜具有由第一绝缘膜形成并从沟槽的端部延伸至漏极侧的第一部分和由第一绝缘膜和第二绝缘膜构成的第二部分，并且设置在漏电极侧 相对于第一部分。 可以通过减小在漏电极侧的沟槽的端部处的第一部分的厚度来减小导通电阻。

公开(公告)号：US10410868B2

公开(公告)日：2019-09-10

申请号：US15882687

申请日：2018-01-29

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/51 ,  H01L29/40 ,  H01L29/20 ,  H01L21/02 ,  H01L21/308 ,  H01L29/45

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.