公开(公告)号：US20170069661A1

公开(公告)日：2017-03-09

申请号：US14887814

申请日：2015-10-20

申请人： STMicroelectronics, Inc.

发明人： John Hongguang Zhang

IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L21/762 ,  H01L21/84 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

CPC分类号： H01L27/1203 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02675 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/66628

摘要： A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are then converted into a transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are converted into a transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

摘要翻译： 晶体管器件通过在半导体层上生长半导体材料的外延层并在栅极位于的位置处形成延伸穿过外延层的开口来制造。 该开口从外延层提供在开口的一侧上的源极外延区域和在开口的相对侧上的漏极外延区域。 源极外延区域和源极外延区域下面的半导体层的第一部分然后被转换成晶体管源极区域。 此外，漏极外延区域和位于漏极外延区域下方的半导体层的第二部分被转换成晶体管漏极区域。 晶体管源极和漏极区之间的半导体层的第三部分形成晶体管沟道区。 然后在晶体管沟道区域上方的开口中形成晶体管栅电极。

公开(公告)号：US20160351500A1

公开(公告)日：2016-12-01

申请号：US14724975

申请日：2015-05-29

申请人： STMicroelectronics, Inc.

发明人： John Hongguang Zhang

IPC分类号： H01L23/535 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/535

摘要： A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

摘要翻译： 半导体衬底包括掺杂区域。 预金属化电介质层在半导体衬底上延伸。 第一金属化层设置在预金属化电介质层的顶表面上。 金属接触从第一金属化层延伸到掺杂区域。 预金属化介电层包括亚层，第一金属接触由亚接触形成，每个子接触形成在一个子层中。 每个第一子接触件具有宽度和长度，其中形成金属接触件的子接触件的长度彼此不同。

公开(公告)号：US20160308128A1

公开(公告)日：2016-10-20

申请号：US14960712

申请日：2015-12-07

申请人： STMicroelectronics, Inc.

发明人： Qing Liu ,  John Hongguang Zhang

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

摘要： A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

公开(公告)号：US20160064647A1

公开(公告)日：2016-03-03

申请号：US14938432

申请日：2015-11-11

申请人： STMICROELECTRONICS, INC.

发明人： John Hongguang Zhang

IPC分类号： H01L41/332

CPC分类号： H01L41/332 ,  H01L41/0973

摘要： A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.

公开(公告)号：US10074606B2

公开(公告)日：2018-09-11

申请号：US15464487

申请日：2017-03-21

申请人： STMicroelectronics, Inc.

发明人： John Hongguang Zhang

IPC分类号： H01L29/80 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/535

摘要： A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

公开(公告)号：US20180166469A1

公开(公告)日：2018-06-14

申请号：US15890910

申请日：2018-02-07

申请人： STMicroelectronics, Inc.

发明人： John Hongguang Zhang

IPC分类号： H01L27/12 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417

CPC分类号： H01L27/1211 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/845 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

摘要： A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

公开(公告)号：US20170222018A1

公开(公告)日：2017-08-03

申请号：US15485754

申请日：2017-04-12

申请人： STMicroelectronics, Inc.

发明人： John Hongguang Zhang

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L23/528 ,  H01L29/423

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

摘要： An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.

公开(公告)号：US20170194244A1

公开(公告)日：2017-07-06

申请号：US15464487

申请日：2017-03-21

申请人： STMicroelectronics, Inc.

发明人： John Hongguang Zhang

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/535

摘要： A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

公开(公告)号：US09679847B2

公开(公告)日：2017-06-13

申请号：US14734013

申请日：2015-06-09

申请人： STMicroelectronics, Inc.

发明人： John Hongguang Zhang

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

摘要： An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.

公开(公告)号：US09570512B2

公开(公告)日：2017-02-14

申请号：US14960595

申请日：2015-12-07

申请人： STMicroelectronics, Inc.

发明人： Qing Liu ,  John Hongguang Zhang

IPC分类号： H01L21/4763 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

摘要： A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

摘要翻译： 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。