公开(公告)号：US11978772B2

公开(公告)日：2024-05-07

申请号：US17678460

申请日：2022-02-23

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yoshiyuki Kawashima

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

CPC分类号： H01L29/40117 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7832 ,  H01L29/792

摘要： A first gate electrode is formed on a semiconductor substrate via a first insulating film containing a metal element. A sidewall insulating film is formed on a side surface of the first gate electrode. A second gate electrode is formed on the semiconductor substrate via a second insulating film. The second gate electrode is formed so as to adjacent to the first gate electrode via the second insulating film. The second insulating film is made of a stacked film having a third insulating film, a fourth insulating film having a charge accumulating function, and a fifth insulating film. The third insulating film is formed on the semiconductor substrate as a result of an oxidation of a portion of the semiconductor substrate, and formed on the side surface of the first gate electrode as a result of an oxidation of the sidewall insulating film, by the thermal oxidation treatment.

公开(公告)号：US20240128260A1

公开(公告)日：2024-04-18

申请号：US18301303

申请日：2023-04-17

申请人： DB HiTek Co., Ltd.

发明人： Seung Hyun KIM ,  Hee Bae LEE ,  Jae Yuhn MOON ,  Soon Jong PARK

IPC分类号： H01L27/07 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L27/0727 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66893 ,  H01L29/7832 ,  H01L29/872

摘要： Disclosed are a semiconductor device (1) including a MOSPET region and an integrated diode region, and a manufacturing method thereof. More particularly, a semiconductor device (1) including a silicon carbide (SiC) MOSPET region and an integrated Schottky bather diode that reduce forward voltage drop (Vf), device area, and switching oscillation resulting from parasitic inductance are disclosed.

公开(公告)号：US20230378292A1

公开(公告)日：2023-11-23

申请号：US18366002

申请日：2023-08-07

申请人： DENSO CORPORATION

发明人： JUNICHI UEHARA ,  YUSUKE HAYAMA

IPC分类号： H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L29/1608 ,  H01L29/66893 ,  H01L29/7832

摘要： A SiC semiconductor device includes a substrate of a first conductivity type, a buffer layer of the first conductivity type on the substrate, a low-concentration layer on the buffer layer, a first deep layer and a JFET portion on the low-concentration layer, a current diffusion layer of the first conductivity type disposed on the JFET portion and having an impurity concentration higher than the low-concentration layer, a second deep layer of a second conductivity type disposed on the first deep layer, a base layer of the second conductivity type disposed on the current diffusion layer and the second deep layer, an impurity region of the first conductivity type disposed in a surface layer portion of the base layer, and a trench gate structure penetrating the impurity region and the base layer and reach the current diffusion layer. The JFET portion is formed with defect portions.

公开(公告)号：US11688774B2

公开(公告)日：2023-06-27

申请号：US17572825

申请日：2022-01-11

申请人： Monolithic Power Systems, Inc.

发明人： Ignacio Cortes Mayol ,  Philippe Godignon ,  Victor Soler ,  Jose Rebollo

IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808

CPC分类号： H01L29/407 ,  H01L29/66893 ,  H01L29/7832 ,  H01L29/8083

摘要： A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

公开(公告)号：US20230141429A1

公开(公告)日：2023-05-11

申请号：US17883683

申请日：2022-08-09

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI

IPC分类号： H01L29/786 ,  H01L29/24 ,  H01L29/78

CPC分类号： H01L29/7869 ,  H01L29/786 ,  H01L29/24 ,  H01L29/7832 ,  H01L29/78696

摘要： A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.

公开(公告)号：US20180090600A1

公开(公告)日：2018-03-29

申请号：US15671452

申请日：2017-08-08

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Hidemoto TOMITA ,  Masakazu KANECHIKA ,  Hiroyuki UEDA ,  Tomohiko MORI

IPC分类号： H01L29/66 ,  H01L21/02 ,  C30B25/02 ,  C30B29/40

CPC分类号： H01L29/66916 ,  C30B25/02 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/66242 ,  H01L29/66522 ,  H01L29/66712 ,  H01L29/737 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7802 ,  H01L29/7832

摘要： A semiconductor device may include a nitride semiconductor layer, an insulation gate section, and a heterojunction region, wherein the nitride semiconductor layer may include an n-type vertical drift region, a p-type channel region adjoining the vertical drift region, and an n-type source region separated from the vertical drift region by the channel region, wherein the insulation gate section is opposed to a portion of the channel region that separates the vertical drift region and the source region, the heterojunction region is in contact with at least a part of a portion of the vertical drift region that is disposed at the one of main surfaces, and the heterojunction region is an n-type nitride semiconductor or an i-type nitride semiconductor having a bandgap wider than a bandgap of the vertical drift region.

公开(公告)号：US20170222043A1

公开(公告)日：2017-08-03

申请号：US15415958

申请日：2017-01-26

申请人： Infineon Technologies Austria AG

发明人： Franz Hirler ,  Anton Mauder ,  Andreas Meiser ,  Till Schloesser

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L23/495 ,  H01L29/10 ,  H01L29/40

CPC分类号： H01L29/7825 ,  H01L23/49575 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7832 ,  H01L29/7835

摘要： A semiconductor device includes a source region and a drain region of a first conductivity type. The source region and the drain region are arranged in a first direction parallel to a first main surface of a semiconductor substrate. The semiconductor device further includes a layer stack having a drift layer of the first conductivity type and a compensation layer of a second conductivity type. The drain region is electrically connected with the drift layer. The semiconductor device also includes a connection region of the second conductivity type extending into the semiconductor substrate, the connection region being electrically connected with the compensation layer, wherein the buried semiconductor portion does not fully overlap with the drift layer.

公开(公告)号：US20170194474A1

公开(公告)日：2017-07-06

申请号：US15390590

申请日：2016-12-26

申请人： Riichiro Shirota ,  Shinichiro Takatani

发明人： Riichiro Shirota ,  Shinichiro Takatani

IPC分类号： H01L29/778 ,  H01L29/205 ,  H01L29/788 ,  H01L29/423 ,  H01L29/06 ,  H01L29/51 ,  H01L29/792 ,  H01L29/20 ,  H01L29/417

CPC分类号： H01L29/7787 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/517 ,  H01L29/7786 ,  H01L29/7831 ,  H01L29/7832 ,  H01L29/788 ,  H01L29/792

摘要： A nitride semiconductor transistor device is disclosed to provide a normally-off nitride semiconductor transistor device which is excellent in switching properties with less dispersion of the properties. The nitride semiconductor transistor device has a buffer layer, a GaN layer, and an AlGaN layer in turn grown on a substrate. A first insulating film, a charge storage layer, a second insulating film, and a control electrode are in turn grown on the AlGaN layer. A source electrode and a drain electrode are formed to sandwich the charge storage layer over the AlGaN layer. A threshold voltage to shut off an electric current flowing between the source and drain electrodes through a conductive channel induced at an interface of the AlGaN layer and the GaN layer is made positive by adjusting charge stored in the charge storage layer.

公开(公告)号：US09673323B2

公开(公告)日：2017-06-06

申请号：US15004438

申请日：2016-01-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun-Lin Tsai

IPC分类号： H01L21/337 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/06 ,  H03K17/22 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/7832 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H03K17/223

摘要： A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

公开(公告)号：US09525035B2

公开(公告)日：2016-12-20

申请号：US14563706

申请日：2014-12-08

申请人： Texas Instruments Incorporated

发明人： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC分类号： H01L29/40 ,  H01L21/763 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/404 ,  H01L21/763 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/783 ,  H01L29/7832

摘要： A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

摘要翻译： 具有源区域，体接触区域和多个具有场板的沟槽结构的垂直高压MOS晶体管，以及形成MOS晶体管的方法通过减少MOS晶体管的导通电阻来降低 沟渠。 可以通过同时接触源区域，身体接触区域和场板的金属触点来减少沟槽间距。 也可以通过增加LDD区域的尺寸的栅极来减小沟槽间距。