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公开(公告)号：US10062624B2
公开(公告)日：2018-08-28
申请号：US15634472
申请日：2017-06-27
IPC分类号： H01L23/14 , H01L23/13 , H01L23/373 , H01L21/48 , H01L23/00
CPC分类号： H01L23/147 , H01L21/481 , H01L21/4846 , H01L23/13 , H01L23/3738 , H01L24/83 , H01L24/97 , H01L2224/06181 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/32227 , H01L2224/3303 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/1033 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/15153 , H01L2924/157 , H01L2924/00014
摘要： A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
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公开(公告)号：US20160133534A1
公开(公告)日：2016-05-12
申请号：US14534254
申请日：2014-11-06
CPC分类号： H01L23/147 , H01L21/481 , H01L21/4846 , H01L23/13 , H01L23/3738 , H01L24/83 , H01L24/97 , H01L2224/06181 , H01L2224/32225 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/1033 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/15153 , H01L2924/157
摘要： A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
摘要翻译： 封装晶体管器件（100）包括半导体芯片（101），其包括具有分布在第一和相对的第二芯片侧上的端子的晶体管; 以及构成为脊（111）的低等级硅（lg-Si）的板坯（110），其构成包括适于容纳所述芯片的凹陷中心区域的凹陷，所述脊具有在第一平面中的第一表面和所述凹入 中心区域在第二平面中具有与第一平面间隔开至少等于芯片厚度的深度（112）的第二表面，所述脊被设备端子（120; 121）覆盖，所述深度连接到具有 连接第一芯片侧的端子，使得相对的第二芯片侧的端子（103）与板条脊上的装置端子共面。
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公开(公告)号：US08748976B1
公开(公告)日：2014-06-10
申请号：US13787044
申请日：2013-03-06
发明人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Hideaki Kawahara , Hong Yang , Seetharaman Sridhar , Hao Wu , Boling Wen
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0649 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7802
摘要： A semiconductor device contains a vertical MOS transistor with instances of a vertical RESURF trench on opposite sides of a vertical drift region. The vertical RESURF trench contains a dielectric trench liner on sidewalls, and a lower field plate and an upper field plate above the lower field plate. The dielectric trench liner between the lower field plate and the vertical drift region is thicker than between the upper field plate and the vertical drift region. A gate is disposed over the vertical drift region and is separate from the upper field plate. The upper field plate and the lower field plate are electrically coupled to a source electrode of the vertical MOS transistor.
摘要翻译： 半导体器件包含垂直MOS晶体管，其具有在垂直漂移区域的相对侧上的垂直RESURF沟槽的实例。 垂直RESURF沟槽包含侧壁上的电介质沟槽衬垫，下场板上的下场板和上场板。 下场板和垂直漂移区之间的电介质沟槽衬垫比上场板和垂直漂移区之间厚。 栅极设置在垂直漂移区上方并与上场板分离。 上场板和下场板电耦合到垂直MOS晶体管的源电极。
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公开(公告)号：US10672901B2
公开(公告)日：2020-06-02
申请号：US16277719
申请日：2019-02-15
发明人： Hideaki Kawahara , Christopher Boguslaw Kocon , Seetharaman Sridhar , Satoshi Suzuki , Simon John Molloy
摘要： A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
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公开(公告)号：US10573718B2
公开(公告)日：2020-02-25
申请号：US15347325
申请日：2016-11-09
发明人： Christopher Boguslaw Kocon , Simon John Molloy , John Manning Savidge Neilson , Hideaki Kawahara
IPC分类号： H01L29/40 , H01L29/78 , H01L29/08 , H01L29/417 , H01L29/66 , H01L29/06 , H01L21/763 , H01L29/10
摘要： A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.
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公开(公告)号：US10541326B2
公开(公告)日：2020-01-21
申请号：US15622869
申请日：2017-06-14
发明人： Hideaki Kawahara , Seetharaman Sridhar , Christopher Boguslaw Kocon , Simon John Molloy , Hong Yang
摘要： A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.
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公开(公告)号：US20190385992A1
公开(公告)日：2019-12-19
申请号：US16546475
申请日：2019-08-21
发明人： Osvaldo Jorge Lopez , Walter Hans Paul Schroen , Jonathan Almeria Noquil , Thomas Eugene Grebs , Simon John Molloy
IPC分类号： H01L25/16 , H01L25/18 , H01L23/00 , H01L21/50 , H01L23/14 , H01L23/13 , H01L23/06 , H01L23/053 , H01L29/06 , H01L25/00 , H01L31/02 , H01L31/18 , H01L27/088 , H01L27/082 , H01L31/0216 , H01L31/042 , H01L31/028
摘要： A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.
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公开(公告)号：US10438936B2
公开(公告)日：2019-10-08
申请号：US15820246
申请日：2017-11-21
发明人： Osvaldo Jorge Lopez , Walter Hans Paul Schroen , Jonathan Almeria Noquil , Thomas Eugene Grebs , Simon John Molloy
IPC分类号： H01L25/16 , H01L31/028 , H01L31/042 , H01L31/0216 , H01L27/082 , H01L27/088 , H01L31/18 , H01L31/02 , H01L25/00 , H01L23/053 , H01L23/06 , H01L23/13 , H01L23/14 , H01L21/50 , H01L23/00 , H01L25/18 , H01L29/06 , H01L23/498
摘要： A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.
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公开(公告)号：US20170194306A1
公开(公告)日：2017-07-06
申请号：US15465455
申请日：2017-03-21
发明人： Osvaldo Jorge Lopez , Walter Hans Paul Schroen , Jonathan Almeria Noquil , Thomas Eugene Grebs , Simon John Molloy
IPC分类号： H01L25/16 , H01L31/0216 , H01L31/028 , H01L25/00 , H01L31/18 , H01L27/082 , H01L27/088 , H01L31/02 , H01L31/042
CPC分类号： H01L25/167 , H01L21/50 , H01L23/053 , H01L23/06 , H01L23/13 , H01L23/147 , H01L23/49844 , H01L24/83 , H01L25/18 , H01L25/50 , H01L27/082 , H01L27/088 , H01L29/0657 , H01L31/02008 , H01L31/02168 , H01L31/028 , H01L31/042 , H01L31/1804 , H01L31/1868 , H01L2224/83851 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01079 , H01L2924/04642 , H01L2924/04941 , H01L2924/05042 , H01L2924/05442 , H01L2924/10155 , H01L2924/1305 , H01L2924/13091 , H01L2924/1425 , H01L2924/1427 , H01L2924/15
摘要： A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.
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公开(公告)号：US10811533B2
公开(公告)日：2020-10-20
申请号：US15139496
申请日：2016-04-27
发明人： Christopher Boguslaw Kocon , Hideaki Kawahara , Simon John Molloy , Satoshi Suzuki , John Manning Savidge Neilson
IPC分类号： H01L29/78 , H01L29/66 , H01L29/40 , H01L29/423 , H01L29/06 , H01L29/08 , H01L29/786 , H01L21/311 , H01L29/10 , H01L29/417 , H01L29/45
摘要： A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.
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