公开(公告)号：US20240339541A1

公开(公告)日：2024-10-10

申请号：US18745323

申请日：2024-06-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC分类号： H01L29/78 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/7856 ,  H01L21/3065 ,  H01L21/32134 ,  H01L21/76224 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

公开(公告)号：US20240322037A1

公开(公告)日：2024-09-26

申请号：US18651184

申请日：2024-04-30

申请人： Sony Group Corporation

发明人： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R.C. Post

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/7831 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78645 ,  H01L29/42376

摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

公开(公告)号：US12100767B2

公开(公告)日：2024-09-24

申请号：US17669317

申请日：2022-02-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Ta Wu ,  Chii-Ming Wu ,  Shiu-Ko Jangjian ,  Kun-Tzu Lin ,  Lan-Fang Chang

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L29/7856 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/28114 ,  H01L21/28158 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/495 ,  H01L29/513

摘要： A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

公开(公告)号：US20240021693A1

公开(公告)日：2024-01-18

申请号：US18366848

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuei-Lun Lin ,  Yen-Fu Chen ,  Po-Ting Lin ,  Chia-Yuan Chang ,  Xiong-Fei Yu ,  Chi On Chui

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L29/42368 ,  H01L29/7856 ,  H01L21/28194 ,  H01L29/66795 ,  H01L29/513

摘要： A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

公开(公告)号：US20240014324A1

公开(公告)日：2024-01-11

申请号：US17810846

申请日：2022-07-06

申请人： NXP B.V.

发明人： Viet Thanh Dinh ,  Asanga H. Perera ,  Arjan Mels

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/84

CPC分类号： H01L29/7856 ,  H01L29/66803 ,  H01L27/0886 ,  H01L21/823431 ,  H01L21/845

摘要： A semiconductor device and methods of forming the same include a semiconductive fin protruding vertically from a body region and extending along a first direction, an insulator material above the body region and surrounding a lower portion of the fin, and a gap region between first and second ends of the semiconductive fin where at least a top portion of the semiconductive fin is absent. The device includes current terminals coupled to first and second ends of the fin, and a gate electrode and a gate extension coupled to the fin. The gate electrode surrounds the top portion of the semiconductive fin and is separated from the semiconductive by a gate insulator material. The gate extension has a first end adjacent to the gate electrode and a second end above the body region within the gap region.

公开(公告)号：US11817504B2

公开(公告)日：2023-11-14

申请号：US17464517

申请日：2021-09-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Guan-Lin Chen ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L21/762 ,  B82Y10/00 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/7856 ,  H01L21/76229 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/6681 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  B82Y10/00

摘要： A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

公开(公告)号：US20230327023A1

公开(公告)日：2023-10-12

申请号：US18204550

申请日：2023-06-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungmin KIM

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7856 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/36

摘要： A semiconductor device and a method of manufacturing a semiconductor device, the device including a first semiconductor pattern on a substrate, the first semiconductor pattern including a lower channel; a second semiconductor pattern on the first semiconductor pattern and spaced apart from the first semiconductor pattern in a vertical direction, the second semiconductor pattern including an upper channel extending in the vertical direction; a gate electrode covering the lower channel and surrounding the upper channel; and source/drain patterns on opposite sides of the upper channel, wherein the substrate and the first semiconductor pattern have a doping concentration of 1019/cm3 or less.

公开(公告)号：US11784257B2

公开(公告)日：2023-10-10

申请号：US17475196

申请日：2021-09-14

申请人： Intel Corporation

发明人： Bernhard Sell

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L27/092 ,  H10B12/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/7853 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/786 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/7856 ,  H10B12/056 ,  H10B12/36 ,  H01L2924/13067

摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

公开(公告)号：US20230253469A1

公开(公告)日：2023-08-10

申请号：US18137257

申请日：2023-04-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： YU-CHI PAN ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234

CPC分类号： H01L29/42368 ,  H01L29/7856 ,  H01L29/66795 ,  H01L27/0886 ,  H01L29/513 ,  H01L21/28185 ,  H01L21/823821 ,  H01L27/0924 ,  H01L21/823431 ,  H01L29/785 ,  H01L21/31122

摘要： A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.

公开(公告)号：US20190088743A1

公开(公告)日：2019-03-21

申请号：US16195389

申请日：2018-11-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Sheng CHEN ,  Cheng-Hsien WU ,  Chih Chieh YEH ,  Yee-Chia YEO

IPC分类号： H01L29/10 ,  H01L27/088 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7856 ,  H01L29/78696

摘要： A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.