公开(公告)号：US20230387251A1

公开(公告)日：2023-11-30

申请号：US17824690

申请日：2022-05-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tien-Shun CHANG ,  Kuo-Ju CHEN ,  Sih-Jie LIU ,  Wei-Fu WANG ,  Yi-Chao WANG ,  Li-Ting WANG ,  Su-Hao LIU ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/265

摘要： A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.

公开(公告)号：US20230343781A1

公开(公告)日：2023-10-26

申请号：US18215059

申请日：2023-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Wen CHANG ,  Hong-Nien LIN ,  Chien-Hsing LEE ,  Chih-Sheng CHANG ,  Ling_Yen YEH ,  Wilman TSAI ,  Yee-Chia YEO

IPC分类号： H01L27/06 ,  H01L29/417 ,  H01L27/088 ,  H01L21/28 ,  H10B51/30 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L29/41791 ,  H01L27/0886 ,  H01L29/40111 ,  H10B51/30 ,  H01L29/78391 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/7851 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L28/40 ,  H01L29/66545

摘要： A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

公开(公告)号：US20210343705A1

公开(公告)日：2021-11-04

申请号：US17353386

申请日：2021-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Wen CHANG ,  Hong-Nien LIN ,  Chien-Hsing LEE ,  Chih-Sheng CHANG ,  Ling-Yen YEH ,  Wilman TSAI ,  Yee-Chia YEO

IPC分类号： H01L27/06 ,  H01L27/1159 ,  H01L29/417 ,  H01L27/088 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8234 ,  H01L49/02

摘要： A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

公开(公告)号：US20170256615A1

公开(公告)日：2017-09-07

申请号：US15600441

申请日：2017-05-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Sheng Chen ,  Chih Chieh YEH ,  Cheng-Hsien WU ,  Yee-Chia YEO

IPC分类号： H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L27/092

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7856 ,  H01L29/78696

摘要： A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

公开(公告)号：US20240363404A1

公开(公告)日：2024-10-31

申请号：US18767722

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Cheng CHEN ,  Tang-Kuei CHANG ,  Yee-Chia YEO ,  Huicheng CHANG ,  Wei-Wei LIANG ,  Ji CUI ,  Fu-Ming HUANG ,  Kei-Wei CHEN ,  Liang-Yin CHEN

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L21/76859 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/7851

摘要： The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US20240105778A1

公开(公告)日：2024-03-28

申请号：US18526856

申请日：2023-12-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Sheng CHEN ,  Yee-Chia YEO ,  Chih Chieh YEH ,  Cheng-Hsien WU

IPC分类号： H01L29/10 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7856 ,  H01L29/78696 ,  H01L21/82385

摘要： A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

公开(公告)号：US20240030317A1

公开(公告)日：2024-01-25

申请号：US17869205

申请日：2022-07-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Heng-Wen TING ,  Ming-Hua YU ,  Yee-Chia YEO ,  Han-Yu TANG

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/7851 ,  H01L29/0847

摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a semiconductor substrate; forming a gate structure over a first portion of the semiconductor fin; etching a source/drain recess over a second portion of the semiconductor fin; and performing an in-situ source/drain etching and epitaxy process to form a source/drain epitaxial structure in the second portion of the semiconductor fin. The step of performing the in-situ source/drain etching and epitaxy process comprises performing a dry etching process to adjust a profile of the source/drain recess in a chamber; and after adjusting the dry etching process, epitaxially growing the source/drain epitaxial structure in the source/drain recess in the chamber.

公开(公告)号：US20240030312A1

公开(公告)日：2024-01-25

申请号：US17871882

申请日：2022-07-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuo-Ju CHEN ,  Wei-Ting CHANG ,  Po-Kang HO ,  Su-Hao LIU ,  Yee-Chia YEO

IPC分类号： H01L29/66

CPC分类号： H01L29/66545 ,  H01L29/66795

摘要： A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; etching back the dummy gate layer; performing an implantation process to the dummy gate layer to form an implantation region in the dummy gate layer, wherein a vertical thickness of the dummy gate layer is greater than a vertical thickness of the implantation region; forming a patterned hard mask stack over the implantation region; patterning the implantation region and the dummy gate layer by using the patterned hard mask stack as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.

公开(公告)号：US20220165869A1

公开(公告)日：2022-05-26

申请号：US17669688

申请日：2022-02-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chun MA ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

摘要： A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a liner layer and an isolation structure surrounding the fin structure. The structure also includes a gate dielectric layer formed over the fin structure and the isolation structure. The structure also includes a gate structure formed over the gate dielectric layer. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The fin structure includes a protruding portion laterally extending over the liner layer.

公开(公告)号：US20210272952A1

公开(公告)日：2021-09-02

申请号：US17322717

申请日：2021-05-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tung Ying LEE ,  Ziwei FANG ,  Yee-Chia YEO ,  Meng-Hsuan HSIAO

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768 ,  A61B17/285 ,  A61B17/29 ,  A61B17/295 ,  A61B18/14 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66

摘要： In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.