公开(公告)号：US20240429318A1

公开(公告)日：2024-12-26

申请号：US18341384

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Guan-Lin Chen ,  Shi Ning Ju ,  Jung-Chien Cheng

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A vertically protruding structure is formed. The vertically protruding structure includes a substrate, a first semiconductor layer disposed over the substrate, a channel layer disposed over the first semiconductor layer, and a second semiconductor layer disposed over the channel layer. The first semiconductor layer and the second semiconductor layer each contain a first type of semiconductive material. The channel layer contains a second type of semiconductive material different from the first type. First recesses are formed in the first semiconductor layer and the second semiconductor layer. Each of the first recesses protrudes laterally inward. The first recesses are filled with dielectric spacers. The channel layer and the substrate are laterally trimmed. The remaining portions of the channel layer and the dielectric spacers define second recesses that protrude laterally inward. Gate structures are formed in the second recesses.

公开(公告)号：US20240387623A1

公开(公告)日：2024-11-21

申请号：US18787813

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Chien Cheng ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

公开(公告)号：US20240339531A1

公开(公告)日：2024-10-10

申请号：US18365470

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Jung-Chien Cheng ,  Chih-Hao Wang

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes a first base fin and a second base fin extending from a substrate, an isolation feature disposed between the first base fin and the second base fin, a first dummy epitaxial layer disposed on the first base fin, a second dummy epitaxial layer disposed on the second base fin, a first insulator layer over the first dummy epitaxial layer, a second insulator layer over the second dummy epitaxial layer, a first source/drain feature disposed on the first insulator layer, a second source/drain feature disposed on the second insulator layer. A thickness of the first dummy epitaxial layer measured from a top surface of the first base fin is smaller than a thickness of the second dummy epitaxial layer measured from a top surface of the second base fin.

公开(公告)号：US12087636B2

公开(公告)日：2024-09-10

申请号：US17804927

申请日：2022-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Shi Ning Ju ,  Chih-Hao Wang ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0886

Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.

公开(公告)号：US11876119B2

公开(公告)日：2024-01-16

申请号：US17464142

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Chien Cheng ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Jia-Chuan You ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece that includes a substrate, first channel members and second channel members over the substrate, a first gate structure engaging the first channel members, a second gate structure engaging the second channel members, a dielectric fin disposed between the first and second gate structures, an isolation feature disposed under the dielectric fin. The method also includes forming a metal cap layer at the frontside of the workpiece and depositing a dielectric feature on the dielectric fin. The dielectric feature dividing the metal cap layer into a first segment and a second segment. The method also includes etching the isolation feature to form a trench at the backside of the substrate, depositing a spacer on sidewalls of the trench, etching the dielectric fin from the trench, and depositing a seal layer in the trench.

公开(公告)号：US11855078B2

公开(公告)日：2023-12-26

申请号：US17458730

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Jung-Chien Cheng ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823412

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a dielectric feature comprising a first dielectric layer and a second dielectric layer, the first dielectric layer has a first sidewall and a second sidewall opposing the first sidewall, and the second dielectric layer is in contact with at least a portion of the first sidewall and at least a portion of the second sidewall. The structure also includes a first semiconductor layer adjacent the first sidewall, wherein the first semiconductor layer is in contact with the second dielectric layer. The structure further includes a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, wherein the first gate electrode layer has a surface facing the second dielectric layer, and the surface extends over a plane defined by an interface between the second dielectric layer and the first semiconductor layer.

公开(公告)号：US11824058B2

公开(公告)日：2023-11-21

申请号：US18082333

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/28088 ,  H01L21/3086 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The method for forming a semiconductor device includes forming a first stack of channel structures that extends between a source terminal and a drain terminal of a first transistor in a first region of the semiconductor device. The first stack of channel structures includes a first channel structure and a second channel structure. The method further includes forming a first gate structure that wraps around the first stack of channel structures with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.

公开(公告)号：US11817504B2

公开(公告)日：2023-11-14

申请号：US17464517

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Guan-Lin Chen ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L21/762 ,  B82Y10/00 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/7856 ,  H01L21/76229 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/6681 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  B82Y10/00

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

公开(公告)号：US11710737B2

公开(公告)日：2023-07-25

申请号：US17226851

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Chien Cheng ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78696

Abstract: Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

公开(公告)号：US20220328482A1

公开(公告)日：2022-10-13

申请号：US17225907

申请日：2021-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wen-Ting Lan ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin having a first portion having a first width and a second portion having a second width substantially less than the first width. The first portion has a first surface, the second portion has a second surface, and the first and second surfaces are connected by a third surface. The third surface forms an angle with respect to the second surface, and the angle ranges from about 90 degrees to about 130 degrees. The structure further includes a gate electrode layer disposed over the semiconductor fin and source/drain epitaxial features disposed on the semiconductor fin on opposite sides of the gate electrode layer.