公开(公告)号：US12183799B2

公开(公告)日：2024-12-31

申请号：US18447870

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Chien Cheng ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Jia-Chuan You ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a first channel member over a first backside dielectric feature, a first gate structure engaging the first channel member, a second channel member over a second backside dielectric feature, a second gate structure engaging the second channel member, and a first isolation feature includes a first portion laterally between the first and second backside dielectric features and a second portion laterally between the first and second gate structures. The first isolation feature is in physical contact with the first and second gate structures.

公开(公告)号：US12107146B2

公开(公告)日：2024-10-01

申请号：US17394982

申请日：2021-08-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Huan-Chieh Su ,  Jia-Chuan You ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of manufacturing an integrated circuit device including a self-aligned air spacer including the operations of forming a dummy gate, forming a sidewall on the dummy gate, forming a dummy layer on the sidewall, constructing a gate structure within an opening defined by the sidewall, removing at least a portion of the first dummy layer to form a first recess between the sidewall layer and the dummy gate, and capping the first recess to form a first air spacer.

公开(公告)号：US11658244B2

公开(公告)日：2023-05-23

申请号：US17379446

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lin-Yu Huang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/66795

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a contact over a fin structure, a gate spacer layer between the gate stack and the contact, a first mask layer over the gate stack, and a second mask layer over the contact. The first mask layer includes a protruding portion sandwiched between an upper portion of the second mask layer and the gate spacer layer.

公开(公告)号：US10950732B2

公开(公告)日：2021-03-16

申请号：US16235610

申请日：2018-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L21/321 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51

Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a gate structure formed over a substrate. A spacer layer is formed on side portions of the gate structure. A first dielectric layer is formed over the gate structure. A conductive cap layer passes through the first dielectric layer and is formed over the gate structure. A top surface of the conductive cap layer is above a top surface of the spacer layer. The semiconductor device further includes a conductive layer formed over the conductive cap layer. The conductive layer is electrically coupled with the conductive cap layer.

公开(公告)号：US12183733B2

公开(公告)日：2024-12-31

申请号：US18225139

申请日：2023-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Chuan You ,  Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/76 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/94

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

公开(公告)号：US12125912B2

公开(公告)日：2024-10-22

申请号：US18302452

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lin-Yu Huang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/308 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/66795

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact over a source/drain region of a fin structure, a gate stack over a channel region of the fin structure, a first mask layer covering the gate stack, and a second mask layer covering the contact. A side surface of the first mask layer is direct contact with a side surface of the second mask layer, and the first mask layer includes a portion directly below the second mask layer.

公开(公告)号：US11929413B2

公开(公告)日：2024-03-12

申请号：US17871528

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jia-Chuan You ,  Huan-Chieh Su ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7856

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a second gate stack over the second channel structure. The second gate stack has a protruding portion extending away from the second channel structures. The protruding portion of the second gate stack has a second width, and half of the first width is greater than the second width.

公开(公告)号：US20230317810A1

公开(公告)日：2023-10-05

申请号：US17870770

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Chu-Yuan Hsu ,  Guan-Lin Chen ,  Shi Ning JU ,  Jung-Chien CHENG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L27/088 ,  H01L21/823481

Abstract: A device includes: a first vertical stack of nanostructures over a substrate; a second vertical stack of nanostructures over the substrate; a first source/drain region abutting the first vertical stack of nanostructures; a second source/drain region abutting the second vertical stack of nanostructures; a first gate structure wrapping around the nanostructures of the first vertical stack; a second gate structure wrapping around the nanostructures of the second vertical stack; a dielectric layer over the first and second source/drain regions; and an isolation structure that extends from an upper surface of the dielectric layer to a level below upper surfaces of the first and second source/drain regions, the isolation structure being between the first source/drain region and the second source/drain region.

公开(公告)号：US11756958B2

公开(公告)日：2023-09-12

申请号：US17708769

申请日：2022-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Chuan You ,  Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76885 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

公开(公告)号：US11508622B2

公开(公告)日：2022-11-22

申请号：US17120689

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes a gate stack formed across the first fin structure and a first source/drain structure formed over the first fin structure adjacent to the gate stack. The semiconductor device structure further includes a contact structure formed over the first source/drain structure and a dielectric structure formed through the contact structure. In addition, a bottom surface of the contact structure is wider than a top surface of the contact structure.