公开(公告)号：US20250072052A1

公开(公告)日：2025-02-27

申请号：US18410852

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Chun Yi CHOU ,  Guan-Lin CHEN ,  Shi Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.

公开(公告)号：US20240363630A1

公开(公告)日：2024-10-31

申请号：US18770372

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Yi-Ruei JHAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20240047462A1

公开(公告)日：2024-02-08

申请号：US18488337

申请日：2023-10-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng CHING ,  Shi Ning JU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L27/0924 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/4966 ,  H01L29/66553 ,  H01L29/517 ,  H01L21/3086 ,  H01L21/823864 ,  H01L21/823821 ,  H01L21/28088

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first channel structure, a first gate dielectric layer surrounding the first channel structure, and a first metal gate surrounding first gate dielectric layer. The first metal gate includes a first metal layer in direct contact with the first gate dielectric layer and a first metal cap in direct contact with the first gate dielectric layer, wherein the first metal cap is in direct contact with the first metal layer.

公开(公告)号：US20230395599A1

公开(公告)日：2023-12-07

申请号：US18230325

申请日：2023-08-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guan-Lin CHEN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Jung-Chien CHENG ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/786 ,  H01L29/423 ,  H10B10/00

CPC classification number: H01L27/092 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/42392 ,  H10B10/125

Abstract: A method for forming a semiconductor device structure includes forming first, second, and third fin structures from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers, the second fin structure includes a second plurality of semiconductor layers, and the third fin structure includes a third plurality of semiconductor layers, and wherein each of the first, second, and third plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers. The method includes forming an insulating material between the first, second, and third fin structures, forming an end cut in the second fin structure, the end cut exposing an upper portion of the substrate, forming a dielectric fin in the end cut, forming a first dielectric feature on the insulating material and between the first fin structure and the dielectric fin, forming a second dielectric feature on the insulating material and between the dielectric fin structure and the third fin structure, forming a sacrificial gate stack on a portion of the first fin structure, the second fin structure, the third fin structure, the first dielectric feature, and the second dielectric feature, removing a portion of the first fin structure, the third fin structure, and the dielectric fin not covered by the sacrificial gate stack, removing the sacrificial gate stack to expose portions of the first, second, and third fin structures, removing the second semiconductor layers of the first, second, and third plurality of semiconductor layers, and forming a gate electrode layer to surround at least three surfaces of the first semiconductor layers of the first, second, and third plurality of semiconductor layers.

公开(公告)号：US20230223442A1

公开(公告)日：2023-07-13

申请号：US17751573

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Kuo-Cheng CHIANG ,  Shi Ning JU ,  Guan-Lin CHEN ,  Chia-Hao CHANG ,  Chih-Hao WANG

IPC: H01L29/08 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L29/41783

Abstract: A device includes a first vertical stack of nanostructures over a substrate, a second vertical stack of nanostructures over the substrate, a wall structure between and in direct contact with the first and second vertical stacks, a gate structure wrapping around three sides of the nanostructures and a source/drain region beside the first vertical stack of nanostructures.

公开(公告)号：US20240297081A1

公开(公告)日：2024-09-05

申请号：US18646878

申请日：2024-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuan-Ting Pan ,  Yi-Ruei JHAN ,  Chih-Hao WANG ,  Shi Ning JU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78696

Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.

公开(公告)号：US20230317810A1

公开(公告)日：2023-10-05

申请号：US17870770

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Chu-Yuan Hsu ,  Guan-Lin Chen ,  Shi Ning JU ,  Jung-Chien CHENG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L27/088 ,  H01L21/823481

Abstract: A device includes: a first vertical stack of nanostructures over a substrate; a second vertical stack of nanostructures over the substrate; a first source/drain region abutting the first vertical stack of nanostructures; a second source/drain region abutting the second vertical stack of nanostructures; a first gate structure wrapping around the nanostructures of the first vertical stack; a second gate structure wrapping around the nanostructures of the second vertical stack; a dielectric layer over the first and second source/drain regions; and an isolation structure that extends from an upper surface of the dielectric layer to a level below upper surfaces of the first and second source/drain regions, the isolation structure being between the first source/drain region and the second source/drain region.

公开(公告)号：US20220328477A1

公开(公告)日：2022-10-13

申请号：US17225859

申请日：2021-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guan-Lin Chen ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Jung-Chien Cheng ,  CHIH-HAO WANG ,  KUAN-LUN CHENG

IPC: H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

Abstract: A structure includes a first dielectric feature extending along a first direction, the first dielectric feature having a first side and a second side opposing the first side. The structure includes a first semiconductor layer disposed adjacent the first side of the first dielectric feature, the first semiconductor layer extending along a second direction perpendicular to the first direction. The structure includes a CESL in contact with the first dielectric feature and a portion of the first semiconductor layer, an ILD layer in contact with the CESL and a portion of the first semiconductor layer. The structure further includes a second dielectric feature extending along the first direction, the second dielectric feature comprising a first dielectric layer in contact with the CESL and a portion of the first semiconductor layer, and a second dielectric layer in contact with the first dielectric layer and a portion of the first semiconductor layer.

公开(公告)号：US20220293769A1

公开(公告)日：2022-09-15

申请号：US17198777

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Yi-Ruei Jhan ,  KUAN-LUN CHENG ,  CHIH-HAO WANG

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.

公开(公告)号：US20240395880A1

公开(公告)日：2024-11-28

申请号：US18791141

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Chuan YOU ,  Kuan-Ting PAN ,  Shi Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of making a semiconductor device includes manufacturing an active area fin extending in a first direction over a substrate, wherein the active area fin comprises a source region, a drain region, and a channel region between the source region and the drain region. The method includes manufacturing an isolation structure next to the active area fin. The method includes manufacturing isolating fins next to the active area fin and over the isolation structure. The method includes trimming the isolating fins in first fin regions adjacent to the channel regions of the active area fin. The method includes depositing a gate electrode material against the first fin region and the gate dielectric in the channel region.