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    SEMICONDUCTOR CHIP AND FABRICATION METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR CHIP AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20240389346A1

    公开(公告)日：2024-11-21

    申请号：US18788158

    申请日：2024-07-30

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chih-Yu Chang ,  Han-Jong Chia

    IPC: H10B51/30 ,  H01L23/522 ,  H10B12/00 ,  H10B53/40

    Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.

    Integrated circuit including three-dimensional memory device
    3.
    发明授权
    Integrated circuit including three-dimensional memory device 有权

    公开(公告)号：US12137571B2

    公开(公告)日：2024-11-05

    申请号：US18516908

    申请日：2023-11-21

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Bo-Feng Young ,  Yi-Ching Liu ,  Sai-Hooi Yeong ,  Yih Wang ,  Yu-Ming Lin

    IPC: H10B51/40 ,  G11C11/22 ,  H01L23/522 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50 ,  H10B51/20 ,  H10B51/30 ,  H10B51/50

    Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.

    Three dimensional memory device
    4.
    发明授权
    Three dimensional memory device 有权

    公开(公告)号：US12137570B2

    公开(公告)日：2024-11-05

    申请号：US17566313

    申请日：2021-12-30

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chia-Ta Yu ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

    IPC: H10B51/30 ,  H10B51/20

    Abstract: A memory device includes a three dimensional memory array having memory cells arranged on multiple floors in rows and columns. Each column is associated with a bit line and a select line. The memory device further includes select gate pairs each being associated with a column. The bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column and a select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column. The plurality of select gate pairs are formed in a different layer than the plurality of memory cells.

    Semiconductor structure and method of fabricating the same
    7.
    发明授权
    Semiconductor structure and method of fabricating the same 有权

    公开(公告)号：US12114506B2

    公开(公告)日：2024-10-08

    申请号：US18357139

    申请日：2023-07-23

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Shih-Lien Linus Lu ,  Chia-En Huang ,  Yih Wang ,  Yu-Ming Lin

    IPC: H10B51/20 ,  G11C5/06 ,  G11C11/22 ,  H01L23/522

    CPC classification number: H10B51/20 ,  G11C5/06 ,  G11C11/223 ,  H01L23/5221

    Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.

    3D MEMORY WITH GRAPHITE CONDUCTIVE STRIPS
    9.
    发明公开
    3D MEMORY WITH GRAPHITE CONDUCTIVE STRIPS 审中-公开

    公开(公告)号：US20240315033A1

    公开(公告)日：2024-09-19

    申请号：US18677954

    申请日：2024-05-30

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Yu-Ming Lin

    IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H01L23/5221 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    Abstract: A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.

    Memory device and method of forming the same
    10.
    发明授权
    Memory device and method of forming the same 有权

    公开(公告)号：US12089414B2

    公开(公告)日：2024-09-10

    申请号：US17400081

    申请日：2021-08-11

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Shih-Lien Linus Lu ,  Chia-En Huang ,  Yih Wang ,  Yu-Ming Lin

    IPC: H10B51/20 ,  G11C5/06 ,  G11C11/22

    CPC classification number: H10B51/20 ,  G11C5/06 ,  G11C11/223

    Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a multi-layer stack, a plurality of memory cells, and a plurality of conductive contacts. The substrate includes an array region and a staircase region. The multi-layer stack is disposed on the substrate in the array region, wherein the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure. The plurality of memory cells are respectively disposed on sidewalls of the multi-layer stack in the array region, and arranged at least along a stacking direction of the multi-layer stack. The plurality of conductive contacts are respectively on the staircase structure. At least two conductive contacts are electrically connected to each other.

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