公开(公告)号：US12125912B2

公开(公告)日：2024-10-22

申请号：US18302452

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lin-Yu Huang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/308 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/66795

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact over a source/drain region of a fin structure, a gate stack over a channel region of the fin structure, a first mask layer covering the gate stack, and a second mask layer covering the contact. A side surface of the first mask layer is direct contact with a side surface of the second mask layer, and the first mask layer includes a portion directly below the second mask layer.

公开(公告)号：US11715761B2

公开(公告)日：2023-08-01

申请号：US17701345

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tien-Lu Lin ,  Che-Chen Wu ,  Chia-Lin Chuang ,  Yu-Ming Lin ,  Chia-Hao Chang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/764 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/665 ,  H01L29/66545

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a pair of source/drain features formed in a semiconductor substrate and a gate stack formed over a portion of the semiconductor substrate that is between the pair of source/drain features. The semiconductor device structure also includes gate spacers extend along opposing sidewalls of the gate stack and protrude above an upper surface of the gate stack. Additionally, the semiconductor device structure includes a first capping layer formed over the gate stack and spaced apart from the upper surface of the gate stack by a gap. Opposing sidewalls of the first capping layer are covered by portions of the gate spacers that protrude above the upper surface of the gate stack.

公开(公告)号：US11508622B2

公开(公告)日：2022-11-22

申请号：US17120689

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes a gate stack formed across the first fin structure and a first source/drain structure formed over the first fin structure adjacent to the gate stack. The semiconductor device structure further includes a contact structure formed over the first source/drain structure and a dielectric structure formed through the contact structure. In addition, a bottom surface of the contact structure is wider than a top surface of the contact structure.

公开(公告)号：US10109519B2

公开(公告)日：2018-10-23

申请号：US15277100

申请日：2016-09-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Lun Kao ,  Tien-Lu Lin ,  Yung-Chih Wang ,  Cheng-Chi Chuang

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/764 ,  H01L23/532

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A conductive feature over a substrate is provided. A first dielectric layer is deposited over the conductive feature and the substrate. A via-forming-trench (VFT) is formed in the first dielectric layer to expose the conductive feature and the substrate around the conductive feature. The VFT is filled in by a sacrificial layer. A via-opening is formed in the sacrificial layer to expose the conductive feature. A metal plug is formed in the via-opening to connect to the conductive feature. The sacrificial layer is removed to form a surrounding-vacancy around metal plug and the conductive feature. A second dielectric layer is deposited over the substrate to seal a portion of the surrounding-vacancy to form an enclosure-air-gap all around the metal plug and the conductive feature.

公开(公告)号：US09716035B2

公开(公告)日：2017-07-25

申请号：US14310618

申请日：2014-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-I Yang ,  Yung-Chih Wang ,  Cheng-Chi Chuang ,  Chia-Tien Wu ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment semiconductor device includes a substrate and a dielectric layer over the substrate. The dielectric layer includes a first conductive line and a second conductive line. The second conductive line comprises a different conductive material than the first conductive line.

公开(公告)号：US09607881B2

公开(公告)日：2017-03-28

申请号：US14310870

申请日：2014-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Wei Liu ,  Yu-Chieh Liao ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/764 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a structure conductive lines disposed in a base layer and separated by a first region. Pillars are each disposed over a respective one of the conductive lines. A dielectric fill layer is disposed over the pillars and extending between the pillars into the first region, and a void is disposed in the dielectric fill layer in the first region between the conductive lines.

公开(公告)号：US20160358817A1

公开(公告)日：2016-12-08

申请号：US15243572

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-I Yang ,  Hsiang-Wei Liu ,  Chia-Tien Wu ,  Hsiang-Huan Lee ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76843

Abstract: Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.

Abstract translation: 公开了导电元件结构及其制造方法。 在一些实施例中，在绝缘层中形成导电元件的方法包括：在设置在绝缘层上的金属层中形成凹陷; 在所述凹部的侧壁上选择性地形成金属衬垫; 并使用金属层和金属衬垫作为掩模在绝缘层中蚀刻通孔。

公开(公告)号：US20160020168A1

公开(公告)日：2016-01-21

申请号：US14334929

申请日：2014-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Lun Kao ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Jian-Hua Chen ,  Yu-Chieh Liao ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L21/263 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/2633 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device comprises a first rounded metal line in a metallization layer over a substrate, a second rounded metal line in the metallization layer, a first air gap between sidewalls of the first rounded metal line and the second metal line, a first metal line in the metallization layer, wherein a top surface of the first metal line is higher than a top surface of the second rounded metal line and a bottom surface of the first metal line is substantially level with a bottom surface of the second rounded metal line and a second air gap between sidewalls of the second rounded metal line and the first metal line.

Abstract translation: 器件包括在衬底上的金属化层中的第一圆形金属线，金属化层中的第二圆形金属线，第一圆形金属线的侧壁与第二金属线之间的第一气隙， 金属化层，其中第一金属线的顶表面高于第二圆形金属线的顶表面，并且第一金属线的底表面基本上与第二圆形金属线的底表面平齐，第二空气 第二圆形金属线的侧壁与第一金属线之间的间隙。

公开(公告)号：US20150380303A1

公开(公告)日：2015-12-31

申请号：US14319464

申请日：2014-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-I Yang ,  Hsiang-Wei Liu ,  Chia-Tien Wu ,  Hsiang-Huan Lee ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76843

Abstract: Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.

Abstract translation: 公开了导电元件结构及其制造方法。 在一些实施例中，在绝缘层中形成导电元件的方法包括：在设置在绝缘层上的金属层中形成凹陷; 在所述凹部的侧壁上选择性地形成金属衬垫; 并使用金属层和金属衬垫作为掩模在绝缘层中蚀刻通孔。

公开(公告)号：US11978669B2

公开(公告)日：2024-05-07

申请号：US17646901

申请日：2022-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Lin Chuang ,  Chia-Hao Chang ,  Sheng-Tsung Wang ,  Lin-Yu Huang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283

Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.